Presentation on theme: "Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises."— Presentation transcript:
Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises
Suggestions and Warnings Read for detail and comprehension Should be able to complete within normal laboratory period. Make sure you program unused pins as tri-state inputs or you may burnout EPM7128S device on PLDT-2.
Shift Registers Riding without training wheels Riding with training wheels Project 1 -- Basic Component Shift Register as Behavioral VHDL Follow standard steps from project creation to exercise of device Project 2 – Push Button Debounce Count and display debounced presses Count and display non debounced presses Never let inputs float!
Shift Register Entity ENTITY ShftRgstr IS PORT ( Dp: INBIT_VECTOR(7 DOWNTO 0); Ld,Ds, CLK: IN BIT; Q: BUFFER BIT_VECTOR(7 DOWNTO 0)); END ShftRgstr;
Shift Register Architecture ARCHITECTURE Behavioral OF ShftRgstr IS BEGIN PROCESS BEGIN WAIT UNTIL Clk'event AND Clk = '1'; IF Ld = '1' THEN--parallel load Q <= Dp;
Shift Register Architecture ELSE--shift right LSb first Q(0) <= Q(1);--Serial Data Out Q(1) <= Q(2);--Continue Shift Q(2) <= Q(3); Q(3) <= Q(4); Q(4) <= Q(5); Q(5) <= Q(6); Q(6) <= Q(7); Q(7) <= Ds;-- Serial Data In END IF; END PROCESS; END Behavioral;
Vector Waveform Format File Overwrite Clock Arbitrary Value Waveform Editing Tool
Add Push Button Jumper Wires
Bounce on Release
Cross-Coupled NAND gates Requires Two I/O pins Two resistors Double pole switch Output changes on first contact closure
Project 2 – Non Debounce Parallel In from DIP Switches and Debounced Switches Serial Out 5 VDC pb_in (Active-LOW) nPb_in (Active-HIGH) Pb_out (Active-HIGH)