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Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises.

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Presentation on theme: "Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises."— Presentation transcript:

1 Shift-Registers and Push Button Debounce Switching and Logic Lab Standard Laboratory Exercises

2 Suggestions and Warnings Read for detail and comprehension Should be able to complete within normal laboratory period. Make sure you program unused pins as tri-state inputs or you may burnout EPM7128S device on PLDT-2.

3 Shift Registers Riding without training wheels Riding with training wheels Project 1 -- Basic Component Shift Register as Behavioral VHDL Follow standard steps from project creation to exercise of device Project 2 – Push Button Debounce Count and display debounced presses Count and display non debounced presses Never let inputs float!

4 Shift Register Entity ENTITY ShftRgstr IS PORT ( Dp: INBIT_VECTOR(7 DOWNTO 0); Ld,Ds, CLK: IN BIT; Q: BUFFER BIT_VECTOR(7 DOWNTO 0)); END ShftRgstr;

5 Shift Register Architecture ARCHITECTURE Behavioral OF ShftRgstr IS BEGIN PROCESS BEGIN WAIT UNTIL Clk'event AND Clk = '1'; IF Ld = '1' THEN--parallel load Q <= Dp;

6 Shift Register Architecture ELSE--shift right LSb first Q(0) <= Q(1);--Serial Data Out Q(1) <= Q(2);--Continue Shift Q(2) <= Q(3); Q(3) <= Q(4); Q(4) <= Q(5); Q(5) <= Q(6); Q(6) <= Q(7); Q(7) <= Ds;-- Serial Data In END IF; END PROCESS; END Behavioral;

7 Vector Waveform Format File Overwrite Clock Arbitrary Value Waveform Editing Tool

8 Add Push Button Jumper Wires

9 Bounce on Release

10 Cross-Coupled NAND gates Requires Two I/O pins Two resistors Double pole switch Output changes on first contact closure

11 Project 2 – Non Debounce Parallel In from DIP Switches and Debounced Switches Serial Out 5 VDC pb_in (Active-LOW) nPb_in (Active-HIGH) Pb_out (Active-HIGH)

12 Project 2 -- Debounce 4MHz 1KHz pb_in (Active-LOW) nPb_in (Active-HIGH) Pb_out (Active-HIGH)

13 Debouncer Shift Register Load PB_IN CLK != nPb_in = Pb_out Parallel Load nPb_in != Pb_out Shift nPb_in Pb_out

14 Bounce on Press Load PB_IN CLK != nPb_in Pb_out nPB_in Pb_out Load SR4 0… …1 0… …1 1… …1 0… F F F F F…F

15 Bounce on Release Load PB_IN CLK != nPb_in Pb_out nPB_in Pb_out Load SR4 1… …0 1… …0 1… …1 F…F F F E F E F E C …0

16 8 Steps to Success 1. Create Project 2. Capture Logic 3. Analysis and Synthesis 4. Pin Assignments 5. Full Compile 6. Timing Simulation 7. Programming 8. Exercise circuit

17 Unused Pins as Tri-State Inputs Select Assignments Select Device Select Device & Pin Options Select Unused Pins Tab Select As inputs, tri- stated OK


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