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EUMC 1998 Archivierungsangabe An NLTL based Integrated Circuit for a 70-200 GHz VNA System O. Wohlgemuth, B.Agarwal*, R. Pullela*, D. Mensa*, Q. Lee*,

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Presentation on theme: "EUMC 1998 Archivierungsangabe An NLTL based Integrated Circuit for a 70-200 GHz VNA System O. Wohlgemuth, B.Agarwal*, R. Pullela*, D. Mensa*, Q. Lee*,"— Presentation transcript:

1 EUMC 1998 Archivierungsangabe An NLTL based Integrated Circuit for a GHz VNA System O. Wohlgemuth, B.Agarwal*, R. Pullela*, D. Mensa*, Q. Lee*, J. Guthrie*, M. J. W. Rodwell*, R. Reuter, J. Braunstein, M. Schlechtweg, T. Krems, K. Köhler Fraunhofer Institute for Applied Solid State Physics (IAF), Tullastr. 72, D Freiburg - Germany *Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106

2 page 2 Archivierungsangabe Outline Motivation Conventional S-parameter measurement set-up and integration on a chip Design and fabrication Performance of the –integrated components –full chip Summary

3 page 3 Archivierungsangabe Motivation Advancement in III-V technology especially in InP based devices –HEMTs and HBTs with f max > 500 GHz ICs, operating above 120 GHz Presently no commercial broadband on-wafer S-parameter measurement system above 120 GHz available

4 page 4 Archivierungsangabe Measurement System

5 page 5 Archivierungsangabe Block Diagram of the Chip

6 page 6 MD, 26th EuMC 1996 NLTL Limiting faktors: –Bragg Frequency –Skin-effect loss and diode loss

7 page 7 MD, 26th EuMC 1996 Technology Planar Schottky diode process N - layer exponential doped Further process steps: –Interconnect metal, –Si 3 N 4 –Air bridges

8 page 8 MD, 26th EuMC 1996 Problems with High Drive Frequency High skin-effect losses DC walk of because of the high loss –Doides are driven through a minor capacitance variation Only low power available –Long lines neccassary, to reach enough compression

9 page 9 MD, 26th EuMC 1996 Design of the Multiplier NLTL Bragg frequency increases exponential Air bridge line combines wide center conductor with high Bragg frequency Line length: 4.2 mm

10 page 10 Archivierungsangabe Waveform at the Output of the Multiplier NLTL Input: –36 GHz sine wave with 12 dBm power Measured output: –~4.1 ps fall time

11 page 11 MD, 26th EuMC 1996 Directional Coupler Designed for 180 GHz Coupler designed for 10 dB coupling Z even, Z odd,  even and  odd are calculated with a 3D simulator (HFSS) Measured directivity of the coupler using on-wafer sampling circuits

12 page 12 MD, 26th EuMC 1996 Low Pass Filter Low pass filter neccassary with low reflection over the entire bandwidth Z L =75  C choosen for Z eff =50 

13 page 13 MD, 26th EuMC 1996 Nonlinearity of the Sampling Circuits Sampling circuit was driven with a input frequency of 36 GHz Harmonic generation is negligible for input powers below 0 dBm

14 page 14 Archivierungsangabe Power at the DUT Not in the simulation included are: –Attenuation of the sampling circuit –Skin-effect losses of the coupler GHz is sufficient for measuring

15 page 15 MD, 26th EuMC 1996 Measured Directivity of the Full Chip Measurement of 2 Chips –50  (44 +/-1.5  ) chip resistor –open test port

16 page 16 Archivierungsangabe Summary The first IC, which can be used as a S-parameter test set within GHz Design and fabrication Performance of the single components and the full chip Packaging these chips into active probes will permit convenient on-wafer S-parameter measurements This work was supported by the German Ministry BMBF in the frame work of 01BM620 (555339)


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