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Fault Equivalence Number of fault sites in a Boolean gate circuit is = #PI + #gates + # (fanout branches) Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

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**Fault equivalence & collapsing**

Combinational circuits faults f and g are equivalent iff Zf(x) = Zg(x) equivalent faults are not distinguishable For gate with controlling value c and inversion i : all input sac faults and output sa(c i) faults are equivalent

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**Equivalence Rules WIRE/BUFFER sa0 sa0 sa0 sa1 sa0 sa1 sa1 sa1 sa0 sa1**

AND OR sa0 sa1 sa0 sa1 INVERTER sa0 sa1 NOT sa1 sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NAND NOR sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 FANOUT sa1

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**Equivalence Example Faults in red removed by sa0 sa1 equivalence**

collapsing 20 Collapse ratio = = 0.625 32

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Fault Dominance If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. Any set that detects F1 also detects F2 (that dominates F1) When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set.

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**Fault dominace Combinational circuits Example :**

If f dominates g => any test that detects g will also detect f . Therefore, only dominating faults must be detected Example : [x, y]=[1 0] is the only test to detect f1 = y sa1, Since it also detects f2 = z sa0 => f2 dominates x y z

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**Fault dominance & collapsing**

For gate with controlling value c & inversion i, the output sa(c’i) dominates any input sac’ sequential circuits dominance fault collapsing is not useful

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**A dominance collapsed fault set (after equivalence collapsing)**

Dominance Example s-a-1 F1 F2 001 000 101 100 011 All tests of F2 The only test of F1 s-a-0 A dominance collapsed fault set (after equivalence collapsing)

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**MINIMAL SETS OF NON-DOMINATING FAULTS FOR TWO-INPUT GATES**

1 Or equivalently 1 1 1 1 1 1

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**Dominance Example Faults in red removed by equivalence collapsing**

sa0 sa1 Faults in red removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Faults in green removed by dominance collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 15 Collapse ratio = ── = 0.47 32

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**CIRCUIT WITH FANOUT-FREE SUBCIRCUITS SHOWN**

M P L J

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**EXAMPLE OF AN FANOUT-FREE CIRCUIT WITH SET OF DOMINANCE-REDUCED FAULTS**

Equivalent to sa1 at the input b c d e f g h M L Z J 1 a in dominance fault collapsing it is sufficient to consider only the input faults Equivalent to sa0 at the input

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Checkpoint Theorem Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10

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**DOMINANCE-REDUCED FAULT LIST**

x1 b c e f d h g P M L 1 0,1

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**EXAMPLE OF PRUNING AND STRIPPING**

1 d f e b c g J h M P L Unused b f d h J M L

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**The multiple stuck-fault model**

Definition : Let Tg be the set of all tests that detect a fault g, we say that a fault f functionally masks the fault g iff the multiple fault {f, g} is not detected by any test in Tg If f masks g then {f, g} is not detected by t Tg but it may be detected by other tests

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**The multiple stuck-fault model**

Example : Consider the faults c sa0, a sa1 t= 011 is the only test that detects fault c sa0 but t does not detect {c sa0, a sa1} => a sa1 masks c sa0 a b c d 0/1 1 1/0 1/1 if double fault 0 if a single fault

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**The multiple stuck-fault model**

Example : Test set T= {1111, 0111, 1110, 1001, 1010, 0101} detects all SSF in following circuit, but the only test which detects B sa1 and C sa1 is 1001 1 0/1 A B C D 1/0 0/1 1

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**The multiple stuck-fault model**

Example : Using Rajski’s method B sa1 detectable if no A sa0 while C sa1 detected with no conditions 11,00 00,11 01,00,11 A B C D 11,00 01,00,11 00,11 11,00,10 10,00,11 11,00,01

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**The multiple stuck-fault model**

Properties of MSF(Multiple Stuck Faults) in a irredundant two_level circuit , any complete test set for SSF detects all MSF in a fanout-free circuit , any complete test set for SSF detects all double and triple faults & there is a complete test set for SSF that detects all MSF

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**The multiple stuck-fault model**

in an internal fanout-free circuit, any complete test for SSF detects at least 98% of MSF with K < 6 and detects all MSF unless C contains a subcircuit with interconnection A B C D 1/0 0/1 1

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Module 7. In Module 3 we have learned about NAND gate – it is a combination of AND operation followed by NOT operation Symbol A. B = Y Logic Gate.

Module 7. In Module 3 we have learned about NAND gate – it is a combination of AND operation followed by NOT operation Symbol A. B = Y Logic Gate.

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