Download presentation
Published byNickolas Watkins Modified over 3 years ago
1
CPSC 321 Computer Architecture Andreas Klappenecker
Verilog CPSC 321 Computer Architecture Andreas Klappenecker
2
Demux Example 2-to-4 demultiplexer with active low enable a b z[3]
x 1
3
Demux: Structural Model
enable a b z[3] z[2] z[1] z[0] x 1 // 2-to-4 demultiplexer module demux1(z,a,b,enable); input a,b,enable; output [3:0] z; wire abar,bbar; not v0(abar,a), v1(bbar,b); nand (z[0],enable,abar,bbar); nand (z[1],enable,a,bbar); nand (z[2],enable,abar,b); nand (z[3],enable,a,b); endmodule
4
Demux: Dataflow model // 2-to-4 demux // dataflow model module
enable a b z[3] z[2] z[1] z[0] x 1 // 2-to-4 demux // dataflow model module demux2(z,a,b,enable); input a,b,enable; output [3:0] z; assign z[0] = | {~enable,a,b}; assign z[1] = ~(enable & a & ~b); assign z[2] = ~(enable & ~a & b); assign z[3] = enable ? ~(a & b) : 1'b1; endmodule
5
Demux: Behavioral Model
// 2-to-4 demultiplexer with active-low outputs module demux3(z,a,b,enable); input a,b,enable; output [3:0] z; reg z; // not really a register! or b or enable) case ({enable,a,b}) default: z = 4'b1111; 3'b100: z = 4'b1110; 3'b110: z = 4'b1101; 3'b101: z = 4'b1011; 3'b111: z = 4'b0111; endcase endmodule enable a b z[3] z[2] z[1] z[0] x 1
6
Always Blocks The sensitivity … ) contains the events triggering an evaluation of the block @(a or b or c) @(posedge a) @(negedge b) A Verilog compiler evaluates the statements in the always block in the order in which they are written
7
Assignments If a variable is assigned a value in a blocking assignment
a = b & c; then subsequent references to a contain the new value of a Non-blocking assignments <= assigns the value that the variables had while entering the always block
8
D Flip-flop module D_FF(Q,D,clock); output Q; input D, clock; reg Q;
clock) Q <= D; endmodule
9
Clock A sequential circuit will need a clock Clock code fragment
supplied by the testbed Clock code fragment reg clock; parameter period = 100; initial clock 0; clock = ~clock;
10
D-Flipflop with Synchronous Reset
module flipflop(D, Clock, Resetn, Q); input D, Clock, Resetn; output Q; reg Q; Clock) if (!Resetn) Q <= 0; else Q <= D; endmodule // 7.46 in [BV]
11
Gated D-Latch module latch(D, clk, Q) input D, clk; output Q; reg Q;
or clk) if (clk) Q <= D; endmodule Missing else clause => a latch will be synthesized to keep value of Q when clk=0
12
Shift register time D Q1 Q2 t0 1 t1 t2 t3 t4 t5 t6 t7
t1 t2 t3 t4 t5 t6 t7 Q1 Q2 D Q D Q D Clock Positive edge triggered D flip-flops
13
What is wrong here? module example(D,Clock, Q1, Q2) input D, Clock;
output Q1, Q2; reg Q1, Q2; Clock) begin end endmodule Q1 = D; Q2 = Q1; // D=Q1=Q2 Q1 = D; Q2 = Q1;
14
Shift register: Correct Version
module example(D,Clock, Q1, Q2) input D, Clock; output Q1, Q2; reg Q1, Q2; Clock) begin Q1 <= D; Q2 <= Q1; end endmodule
15
Rule of Thumb Blocking assignments are used to describe combinatorial circuits Non-blocking assignments are used in sequential circuits
16
n-bit Ripple Carry Adder
module ripple(cin, X, Y, S, cout); parameter n = 4; input cin; input [n-1:0] X, Y; output [n-1:0] S; output cout; reg [n-1:0] S; reg [n:0] C; reg cout; integer k; or Y or cin) begin C[0] = cin; for(k = 0; k <= n-1; k=k+1) S[k] = X[k]^Y[k]^C[k]; C[k+1] = (X[k] & Y[k]) |(C[k]&X[k])|(C[k]&Y[k]); end cout = C[n]; endmodule
17
Loops and Integers The for loop is used to instantiate hardware modules The integer k simply keeps track of instantiated hardware Do not confuse integers with reg variables
18
Bit-Counter Count the number of bits having value 1 in register X
Again an example for parameters Another example of a for loop
19
Bit Counter module bit_cnt(X,Count); parameter n = 4;
parameter logn = 2; input [n-1:0] X; output [logn:0] Count; reg [logn:0] Count; integer k; begin Count = 0; for(k=0;k<n;k= k+1) Count=Count+X[k]; end endmodule
Similar presentations
© 2018 SlidePlayer.com Inc.
All rights reserved.
English ppt on reported speech Ppt on domain name system Ppt on case study research Ppt on accounting standards 10 Ppt on switching networks Signal generator and display ppt on ipad Ppt on two point perspective lesson Ppt on exim bank of india Ppt on pirates of silicon valley Ppt on solar energy generation