Presentation is loading. Please wait.

Presentation is loading. Please wait.

Verilog CPSC 321 Computer Architecture Andreas Klappenecker.

Similar presentations


Presentation on theme: "Verilog CPSC 321 Computer Architecture Andreas Klappenecker."— Presentation transcript:

1

2 Verilog CPSC 321 Computer Architecture Andreas Klappenecker

3 Demux Example 2-to-4 demultiplexer with active low enableabz[3]z[2]z[1]z[0] 0xx

4 Demux: Structural Model // 2-to-4 demultiplexer module demux1(z,a,b,enable); input a,b,enable; output [3:0] z; wire abar,bbar; not v0(abar,a), v1(bbar,b); nand (z[0],enable,abar,bbar); nand (z[1],enable,a,bbar); nand (z[2],enable,abar,b); nand (z[3],enable,a,b); endmodule enableabz[3]z[2]z[1]z[0] 0xx

5 Demux: Dataflow model // 2-to-4 demux // dataflow model module demux2(z,a,b,enable); input a,b,enable; output [3:0] z; assign z[0] = | {~enable,a,b}; assign z[1] = ~(enable & a & ~b); assign z[2] = ~(enable & ~a & b); assign z[3] = enable ? ~(a & b) : 1'b1; endmodule enableabz[3]z[2]z[1]z[0] 0xx

6 Demux: Behavioral Model // 2-to-4 demultiplexer with active-low outputs module demux3(z,a,b,enable); input a,b,enable; output [3:0] z; reg z; // not really a register! or b or enable) case ({enable,a,b}) default: z = 4'b1111; 3'b100: z = 4'b1110; 3'b110: z = 4'b1101; 3'b101: z = 4'b1011; 3'b111: z = 4'b0111; endcase endmodule enableabz[3]z[2]z[1]z[0] 0xx

7 Always Blocks The sensitivity … ) contains the events triggering an evaluation of the or b or b) A Verilog compiler evaluates the statements in the always block in the order in which they are written

8 Assignments If a variable is assigned a value in a blocking assignment a = b & c; then subsequent references to a contain the new value of a Non-blocking assignments <= assigns the value that the variables had while entering the always block

9 D Flip-flop module D_FF(Q,D,clock); output Q; input D, clock; reg Q; clock) Q <= D; endmodule

10 Clock A sequential circuit will need a clock supplied by the testbed Clock code fragment reg clock; parameter period = 100; initial clock 0; clock = ~clock;

11 D-Flipflop with Synchronous Reset module flipflop(D, Clock, Resetn, Q); input D, Clock, Resetn; output Q; reg Q; Clock) if (!Resetn) Q <= 0; else Q <= D; endmodule // 7.46 in [BV]

12 module latch(D, clk, Q) input D, clk; output Q; reg Q; or clk) if (clk) Q <= D; endmodule Missing else clause => a latch will be synthesized to keep value of Q when clk=0 Gated D-Latch

13 Shift register DQ Q DQ Q D Clock Q1 Q2 Positive edge triggered D flip-flops timeDQ1Q2 t0100 t1010 t2001 t3100 t4110 t5111 t6011 t7001

14 module example(D,Clock, Q1, Q2) input D, Clock; output Q1, Q2; reg Q1, Q2; Clock) begin end endmodule What is wrong here? Q1 = D; Q2 = Q1; Q1 = D; Q2 = Q1; // D=Q1=Q2

15 Shift register: Correct Version module example(D,Clock, Q1, Q2) input D, Clock; output Q1, Q2; reg Q1, Q2; Clock) begin Q1 <= D; Q2 <= Q1; end endmodule

16 Rule of Thumb Blocking assignments are used to describe combinatorial circuits Non-blocking assignments are used in sequential circuits

17 n-bit Ripple Carry Adder module ripple(cin, X, Y, S, cout); parameter n = 4; input cin; input [n-1:0] X, Y; output [n-1:0] S; output cout; reg [n-1:0] S; reg [n:0] C; reg cout; integer k; or Y or cin) begin C[0] = cin; for(k = 0; k <= n-1; k=k+1) begin S[k] = X[k]^Y[k]^C[k]; C[k+1] = (X[k] & Y[k]) |(C[k]&X[k])|(C[k]&Y[k]); end cout = C[n]; end endmodule

18 Loops and Integers The for loop is used to instantiate hardware modules The integer k simply keeps track of instantiated hardware Do not confuse integers with reg variables

19 Bit-Counter Count the number of bits having value 1 in register X Again an example for parameters Another example of a for loop

20 Bit Counter module bit_cnt(X,Count); parameter n = 4; parameter logn = 2; input [n-1:0] X; output [logn:0] Count; reg [logn:0] Count; integer k; begin Count = 0; for(k=0;k


Download ppt "Verilog CPSC 321 Computer Architecture Andreas Klappenecker."

Similar presentations


Ads by Google