2Today’s Topics Lab preview: Verilog styles for FSM “Debouncing” a switchVerilog styles for FSMDon’t forget to check synthesis output and console msgs.State machine stylesMoore vs. Mealy
3Lab Preview: Buttons and Debouncing Mechanical switches “bounce”vibrations cause them to go to 1 and 0 a number of timescalled “chatter”hundreds of times!We want to do 2 things:“Debounce”: Any ideas?Synchronize with clocki.e., only need to look at it at the next +ve edge of clockThink about (for Wed class):What does it mean to “press the button”? Think carefully!!What if button is held down for a long time?
5Verilog coding stylesFirst: More on Verilog procedural/behavioral statementsif-then-elsecase statementThen: How to specify an FSMUsing two always blocksUsing a single always block??Using three always blocks
6Verilog procedural statements All variables/signals assigned in an always statement must be declared as regUnfortunately, the language designers made things unnecessarily complicatednot every signal declared as reg is actually registeredit is possible to declare reg X, even when X is the output of a combinational function, and does not need a register!whattt???!!They thought it would be awesome to let the Verilog compiler figure out if a function is combinational or sequential!a real pain sometimesyou will suffer through it later in the semester if not careful!
7Verilog procedural statements These statements are often convenient:if / elsecase, casezmore convenient than “? : ” conditional expressionsespecially when deeply nestedBut: these must be used only inside always blocksagain, some genius decided thatResult:designers often do this:declare a combinational output as reg Xso they can use if/else/case statements to assign to XHOPE the Verilog compiler will optimize away the unintended latch/reg
8Example: Comb. Logic using case module decto7seg(input [3:0] data,output reg [7:0] segments); // reg is optimized awaycase (data)// abcdefgp0: segments <= 8'b ;1: segments <= 8'b ;2: segments <= 8'b ;3: segments <= 8'b ;4: segments <= 8'b ;5: segments <= 8'b ;6: segments <= 8'b ;7: segments <= 8'b ;8: segments <= 8'b ;9: segments <= 8'b ;default: segments <= 8'b ; // requiredendcaseendmoduleNote the *:it means that when any inputs used in the body of the always block change.This include “data”
9Beware the unintended latch! Very easy to unintentionally specify a latch/register in Verilog!how does it arise?you forgot to define output for some input combinationin order for a case statement to imply combinational logic, all possible input combinations must be describedone of the most common mistakes!one of the biggest sources of headache!you will do it a gazillion timesthis is yet another result of the the hangover of software programmingforgetting everything in hardware runs in parallel, and time is continuousSolutiongood programming practiceremember to use a default statement with casesevery if must have a matching elsecheck synthesizer output / console messages
10Beware the unintended latch! Example: multiplexerout is output of combinational blockno latch/register is intended in this circuitrecommended Verilog:assign out = select? A : B;But, an if statement (inside an always block) will incorrectly introduce a reg:if (select) out <= A;if (!select) out <= B;reg added to save old value if condition is falseto avoid extra reg, cover all cases within one statement:else out <= B;selectABout
11Combinational Logic using casez casez allows case patterns to use don’t caresmodule priority_casez(input [3:0] a,output reg [3:0] y);// reg will be optimized awaycasez(a)4'b1???: y <= 4'b1000; // ? = don’t care4'b01??: y <= 4'b0100;4'b001?: y <= 4'b0010;4'b0001: y <= 4'b0001;default: y <= 4'b0000;endcaseendmodule
12Blocking vs. Nonblocking Assignments (review) <= is a “nonblocking assignment”Occurs simultaneously with others= is a “blocking assignment”Occurs in the order it appears in the file// nonblocking assignmentsmodule syncgood(input clk,input d,output reg q);reg n1;clk)beginn1 <= d; // nonblockingq <= n1; // nonblockingendendmodule// blocking assignmentsmodule syncbad(input clk,input d,output reg q);reg n1;clk)beginn1 = d; // blockingq = n1; // blockingendendmodule
13Cheat Sheet for comb. vs seq. logic Sequential logic:Use clk)Use nonblocking assignments (<=)Do not make assignments to the same signal in more than one always block!e.g.:(posedge clk)q <= d; // nonblocking
14Cheat Sheet for comb. vs seq. logic Combinational logic:Use continuous assignments (assign …) whenever readableassign y = a & b;ORUse (*)All variables must be assigned in every situation!must have a default case in case statementmust have a closing else in an if statementdo not make assignments to the same signal in more than one always or assign statement
15Revisit the sequence recognizer (from last lecture)
16Let’s encode states using localparam module seq_rec (input CLK,input RESET, input X,output reg Z);reg [1:0] state;localparam A = 2'b00, B = 2'b01,C = 2'b10, D = 2'b11;Notice that we have assigned codes to the states.localparam is more appropriate here than parameter because these constants should be invisible/inaccessible to parent module.
18Register for storing state Register with resetsynchronous reset (Lab 5)reset occurs only at clock transitionCLK)if (RESET == 1) state <= A;else state <= next_state;prefer synchronous resetasynchronous resetreset occurs whenever RESET goes highCLK or posedge RESET)use asynchronous reset only if you really need it!Notice that state only gets updatedon posedge of clock (or on reset)
19Output always @(*) case(state) A: Z <= 0; B: Z <= 0; // Z declared as: output reg Z// reg is optimized awaycase(state)A: Z <= 0;B: Z <= 0;C: Z <= 0;D: Z <= X ? 1 : 0;default: Z <= 0;endcase
20Comment on Code Could shorten it somewhat Template helps synthesizer Don’t need three always clausesAlthough it’s clearer to have combinational code be separateDon’t need next_state, for exampleCan just set state on clockTemplate helps synthesizerCheck to see whether your state machines were recognized
21Verilog: specifying FSM using 2 blocks Let us divide FSM into two modulesone stores and update stateanother produces outputs
22Verilog: specifying FSM using 2 blocks reg [1:0] state; reg outp;…clk)case (state)s1: if (x1 == 1'b1) state <= s2;else state <= s3;s2: state <= s4;s3: state <= s4;s4: state <= s1;endcase //default not required for seq logic!s1: outp <= 1'b1;s2: outp <= 1'b1;s3: outp <= 1'b0;s4: outp <= 1'b0;default: outp <= 1'b0; //default required for comb logic!endcase
23Synthesis (see console output) Synthesizing Unit <v_fsm_2>.Related source file is "v_fsm_2.v".Found finite state machine <FSM_0> for signal <state>.| States | || Transitions | || Inputs | || Outputs | || Clock | clk (rising_edge) || Reset | reset (positive) || Reset type | asynchronous || Reset State | || Power Up State | || Encoding | automatic || Implementation | LUT |Summary:inferred 1 Finite State Machine(s).Unit <v_fsm_2> synthesized.
24Incorrect: Putting all in one always Using one always blockgenerally incorrect! (But may work for Moore FSMs)ends up with unintended registers for outputs!clk)case (state)s1: if (x1 == 1'b1) begin state <= s2; outp <= 1'b1; endelse begin state <= s3; outp <= 1'b0; ends2: beginstate <= s4; outp <= 1'b1;ends3: beginstate <= s4; outp <= 1'b0;s4: beginstate <= s1; outp <= 1'b0;endcase
25Synthesis Output Synthesizing Unit <v_fsm_1>. Related source file is "v_fsm_1.v".Found finite state machine <FSM_0> for signal <state>.| States | || Transitions | || Inputs | || Outputs | || Clock | clk (rising_edge) || Reset | reset (positive) || Reset type | asynchronous || Reset State | || Power Up State | || Encoding | automatic || Implementation | LUT |Found 1-bit register for signal <outp>.Summary:inferred 1 Finite State Machine(s).inferred 1 D-type flip-flop(s).
28Synthesis (again, no unintended latch) Synthesizing Unit <v_fsm_3>.Related source file is "v_fsm_3.v".Found finite state machine <FSM_0> for signal <state>.| States | || Transitions | || Inputs | || Outputs | || Clock | clk (rising_edge) || Reset | reset (positive) || Reset type | asynchronous || Reset State | || Power Up State | || Encoding | automatic || Implementation | LUT |Summary:inferred 1 Finite State Machine(s).Unit <v_fsm_3> synthesized.
29My Preference The one with 3 always blocks Follow my template Easy to visualize the state transitionsFor really simple state machines:2 always blocks is okay tooNever put everything into 1 always block!Follow my templatefsm_3blocktemplate.v (posted on the website)
30Moore vs. Mealy FSMs?So, is there a practical difference?
31Moore vs. Mealy Recognizer Mealy FSM: arcs indicate input/output