# 1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

## Presentation on theme: "1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System."— Presentation transcript:

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

2 Workshop 12 – Data flow Modeling Continuous assignments Implicit Continuous Assignment Implicit Net Declaration Delays Regular Assignment Delay Implicit continuous assignment delay Net declaration delay Conditional Operator

3 Data Flow Modeling Data Flow Modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how the design processes data. logic synthesis tools are used to create a Gate-Level circuit from the data flow design description. In the digital design community, the term Register Transfer Level (RTL) design is commonly used for a combination of Data Flow modeling and Behavioral modeling.

4 Continuous Assignments There are two type of assignments in Verilog:  Continuous assignments.  Procedural assignments. Continuous assignments are used outside sequential blocks and can be applied only on nets. Procedural assignments can be used in sequential blocks only. Can be applied on regs not on nets. Continuous assignment is an abstract model of combinational HW driving values onto nets. Continuous assignment keyword assign Continuous assignment is always active. If any input to the assign statement, changes at any time, the assign statement will be re-evaluated and the output will be propagated.

5 Continuous Assignements cont. ● Syntax: assign #delay = ; ● Where to write them: ● Outside procedures ● Inside a module ● Properties: ● They all execute in parallel ● Are order independent ● Are continuously active // optionalnet type !!

6 Regular Continuous assignment examples assign #5 a = b ; // 5 time units delay assign #(5,4) a = b ; // 5 (rise), 4 (fall) time units delays assign {a,b} = {c,d} ; // concatenation assign a[5:3] = b[2:0] ; // sub-vectors connections assign out = in1 & in2 ; // out is a net, i1 and i2 are nets assign addit[15:0] = addit1[15:0] ^ addit2[15:0] ; /* Continuous assign for vector nets, addit is a 16 bit vector net. addi1 and addit2 are 16-bit vector registers */ assign {cout, sum[3:0]} = a[3:0] + b[3:0] + cin ; /* Left-hand side is a concatenation of a scalar net and a vector net

7 Continuous Assignment example - Adders module Half_Adder(sum, carry, A, B) ; input A, B ; output sum, carry ; /* Verilog default to a net data type on the left-hand side of any continuous assignment */ assign sum = (~A&B) + (A&~B) ; assign carry = A&B ; endmodule module Full_Adder (Cout, Sum, A, B, Cin) ; output Cout, Sum ; // default to a net data type input A, B, Cin ; assign Sum = A ^ B ^ Cin ; assign Cout = (A & B) | (B & Cin) | (A & Cin) ; endmodule

8 1-bit Comparator example module Compare1(A, B, Equal, Alarger, Blarger) ; input A, B ; output Equal, Alarger, Blarger ; assign Equal = (A & B) | (~A & ~B) ; assign Alarger = (A & ~B) ; assign Blarger = (~A & B) ; endmodule A B Alarger Blarger Equal Compare1

9 Implicit Continuous Assignment / Net Declaration Implicit Continuous Assignment Verilog provides a shortcut by which a continuous assignment can be placed on a net when it is declared. Example: wire out ; // regular continuous assignment. declare a net assign out = in1 & in2 ; // continuous assignment on the net wire out = in1 & in2 ; // = implicit continuous assignment Implicit Net Declaration wire in1, in2 ; assign out = in1 & in2 ; /* out not declared as a net but an implicit net declaration is inferred for that signal name */ If the net is connected to the module port, the width of the inferred net is equal to the width of the module port.

10 Delays Nets do not store values but they inflict signal delays. # indicates delay and value. Delay can specify both rise and fall times. #(, ) Delay values control the time between the change in any of the right-hand-side operands (input signals) and when the new value is assigned to the left-hand side. Delay types: 1. Regular assignment delay. 2. Implicit continuous assignment delay. 3. Net declaration delay

11 Delay types 1. Regular Assignment Delay Delay value is specified after the keyword assign. Any change in one of the input signals, will be reflected on the output net, times later. An input pulse shorter than the assignment delay, does not propagate to the output. Example: assign #10 out = in1 & in2 ; 2. Implicit continuous assignment delay Used to specify both delay and an assignment on the net. wire #10 out = in1 & in2 ; // same as: wire out ; assign #10 out = in1 & in2 ; 3. Net declaration delay A delay can be specified on a net when declared without putting continuous assignment on the net. wire #10 out ; assign out = in1 & in2 ;

12 Conditional Operator – Conditional Assignment ● Conditional Operators are frequently used in dataflow modeling to model conditional assignments. The conditional expression acts as a switching control. ● The Conditional Operator ( ? : ) takes three operands. Usage: condition_expr ? true_expr : false_expr ; ● The condition_expr is first evaluated. If the result is true (logical 1) then the true_expr is evaluated. If the result is false (logical 0) then the false_expr is evaluated. ● The action of a conditional operator is similar to a multiplexer.

13 Conditional Assignment examples // model functionality of a tri-state buffer assign addr_bus = drive_enable ? Addr_out : 32’bZ ; // model functionality of a 2-to-1 mux assign out = control ? in1 : in0 ; // more elegant than: assign out = (control & in1) | (~ control & in0) ; ● Conditional operators can be nested. Each true_expr or false_expr can itself be conditional operation. // Nested condition operator (4:1 mux). Input [1:0] sel ; assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0) ;

14 Exercise 4 Implement 7- Segment Decoder, in dataflow modeling. Description: converter between Hex number to 7-Segment Display. Applying a low logic level to a segment, will light it up and applying high logic level turns it off. Write the code for the module and its Test Bench.

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