1. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 1 ECE 406 Design of Complex Digital Systems Lecture 10: 9: State Machines & Reset Behavior Spring 2006 2007 W. Rhett Davis NC State University with significant material from Paul Franzon & Bill Allen

2. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 2 Summary of Lecture 8 l How do you model a flip-flop? l What is the difference between blocking and non-blocking assignments? l How do you infer flip-flops for an always@(posedge clock) procedure with blocking or non-blocking assignments? l Is it better to use blocking or non-blocking assignments in an always@(posedge clock) procedure? Why?

3. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 3 Summary of Lecture 8 l What are the key elements of the “simplified coding stlye”? l What Verilog constructs do you use to describe » MUXes » Control logic » Datapath logic » Registers

4. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 4 Today’s Lecture l State Machine Design (1.3.1, 2.6) l Using Reset Signals (1.3.2) l Data Converter Example

5. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 5 State Machine Design l This is a state- transition diagram l If you were asked to design a state- machine to implement this diagram, how would you do it?

6. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 6 Generalized State Machines l “Mealy Machine” » Most general » outputs labeled on transitions

7. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 7 Moore Machine l Less General l Output depends on current state only

8. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 8 State Machine Design l Step 1: Assign States l Step 2: Create the state- register l Step 3: Write a combinational procedure to implement the state- update logic and output logic reg current_state, next_state; always@(posedge clock) current_state <= next_state; always@(in or current_state) case (current_state) 0: if (in) next_state <= 0; else next_state <= 1; 1: if (in) next_state <= 2; else next_state <= 0; 2: next_state <= 0; default: next_state <= 0; endcase

9. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 9 Sophisticated Style State Machine l Could you implement the output logic with this same always@ block? reg state; always@(posedge clock) case (state) 0: if (in) state <= 0; else state <= 1; 1: if (in) state <= 2; else state <= 0; 2: state <= 0; default: state <= 0; endcase

10. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 10 Today’s Lecture l State Machine Design (1.3.1, 2.6) l Using Reset Signals (1.3.2) l Data Converter Example

11. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 11 Reset Signals l At the start of the simulation, state has the value X l What will the next state be? l Will this be the case with synthesized hardware? reg state; always@(posedge clock) case (state) 0: if (in) state <= 0; else state <= 1; 1: if (in) state <= 2; else state <= 0; 2: state <= 0; default: state <= 0; endcase

12. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 12 Rules for Reset Signals l Only the edges for the clock and reset should be in sensitivity list l Reset condition should be specified first l No condition should be made on the clock

13. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 13 Types of Reset Signals l Asynchronous: Reset happens as soon as reset signal is asserted l Synchronous: Reset is synchronized to clock always@(posedge clock or posedge reset) if (reset) value <= 0; else value <= next_value; always@(posedge clock) if (reset) value <= 0; else value <= next_value; Active-high reset

14. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 14 Active-Low Reset l How would you implement an active-low asynchronous reset? WARNING: Popular Exam Question!

15. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 15 Resetting the State Machine l We generally prefer synchronous resets to asynchronous, so that we don’t have to worry about the relative timing of the two signals reg state; always@(posedge clock) if (reset) state <= 0; else case (state) 0: if (in) state <= 0; else state <= 1; 1: if (in) state <= 2; else state <= 0; 2: state <= 0; default: state <= 0; endcase

16. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 16 Today’s Lecture l State Machine Design (1.3.1, 2.6) l Using Reset Signals (1.3.2) l Data Converter Example

17. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 17 Data Converter Specification l When a new 32-bit data word arrives at the input, the module stores it and then outputs the word as 4 bytes, starting with the MSB and ending with the LSB. l The arrival of a 32-bit word to be converted is signaled by a pulse on ready that is 3 clock cycles long. l The output of a byte of data is signaled by a one clock cycle pulse on new. The output byte is available during the new pulse and for one clock cycle after. Data Converter IN ready OUT new 32 / 8 /

18. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 18 Design Process l Step 1: Write Specification l Step 2: Draw Schematic » Ports » Registers » Datapath Logic » MUXes » Control Logic l Step 3: Write Verilog Code » Label Internal Signals » Map elements from schematic into code

19. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 19 Data Selector Schematic

20. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 20 Controller State Diagram

21. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 21 Data Converter (Simplified Style) module dataconv(IN, clock, ready, reset, OUT, new); input clock,reset,ready; input [31:0] IN; output [7:0] OUT; output new; Complete the module description

22. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 22 Data Converter (Simplified Style)

23. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 23 Data Converter (Simplified Style)

24. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 24 Data Converter (Sophisticated Style) module dataconv(IN, clock, ready, reset, OUT, new); input clock,reset,ready; input [31:0] IN; output [7:0] OUT; output new; reg [7:0] OUT; reg new; reg [31:0] value; reg [3:0] state; always @(posedge clock) begin if (reset) state <= 0; else case(state) 0: begin if (ready) state <= 1; else state <= 0; new <= 0; end 1: begin state <= 2; value <= IN; end 2: begin state <= 3; OUT <= value[31:24]; new <= 1; end

25. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 25 Data Converter (Sophisticated Style) 3: begin state <= 4; new <= 0; end 4: begin state <= 5; OUT <= value[23:16]; new <= 1; end 5: begin state <= 6; new <= 0; end 6: begin state <= 7; OUT <= value[15:8]; new <= 1; end 7: begin state <= 8; new <= 0; end 8: begin state <= 9; OUT <= value[7:0]; new <= 1; end 9: begin state <= 0; new <= 0; end default: begin state <= 0; end endcase end endmodule

26. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 26 Comparison of Styles l What will be the difference between the hardware synthesized from the simplified and sophisticated versions of the Data Converter code given in class?

27. Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 27 Summary l How do you implement a state-machine when given a state-transition diagram? l Why in general do you need a reset-signal for a module? l What is the difference between synchronous and asynchronous reset signals?