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1 CS/COE0447 Computer Organization & Assembly Language Chapter 2 Part 1

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2 Topics to cover in Chapter 2 MIPS operations and operands MIPS registers Memory view Instruction encoding Arithmetic operations Logic operations Memory transfer operations

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3 MIPS Operations/Operands “Operation” (instruction) “Operand” MIPS operations –Arithmetic operations (integer/floating-point) (add, sub,…) –Logical operations (and, or,…) –Shift operations (shift a certain number of bits to the left or right) –Compare operations (do something if one operand is less than another,…) –Load/stores to transfer data from/to memory –Branch/jump operations –System control operations/coprocessor operations MIPS operands –General-purpose registers –Fixed registers, e.g., HI/LO registers –Memory location –Immediate value

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4 MIPS Arithmetic All arithmetic instructions have 3 operands –Operand order is fixed: destination first –32 registers (page 2 of green card) Examples –add $t0, $s0, $s2# $t0 = $s0 + $s2 –sub $s0, $t0, $t1# $s0 = $t0 – $t1 rd rs rt

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5 MIPS Registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 $zero $at $v0 $v1 $a0 $a1 $a2 $a3 $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7 HI LO PC $s1 $s2 $s3 $s4 $s5 $s6 $s7 $t8 $t9 $k0 $k1 $gp $sp $fp $ra $s0 General-Purpose RegistersSpecial-Purpose Registers 32 bits

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6 General-Purpose Registers GPR: all can be used as operands in instructions Still, conventions and limitations exist to keep GPRs from being used arbitrarily –r0, termed $zero, always has a value “0” –r31, termed $ra (return address), is reserved for subroutine call/return –Etc. (we’ll see otherc conventsion/limitations later) –Register usage and related software conventions are summarized in “application binary interface” (ABI), which is important when writing system software such as an assembler and a compiler

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7 Instruction Encoding Instructions are encoded in binary numbers –Assembler translates assembly programs into binary numbers –Machine decodes binary numbers to figure out what the instruction is –MIPS has “fixed” 32-bit instruction encoding MIPS has several instruction formats –R-format: arithmetic instructions –I-format: transfer/branch/immediate format –J-format: jump instruction format –(FI/FR-format: floating-point instruction format)(later chapter)

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8 MIPS Instruction Formats NameFieldsComments 6 bits5 bits 6 bitsAll MIPS instructions 32 bits R-formatoprsrtrdshamtfunctArithmetic/logic instruction format I-formatoprsrtaddress/immediateTransfer, branch, immediate format J-formatoptarget addressJump instruction format

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9 R-Format Instructions Define “fields” of the following number of bits each: = opcodersrtrdfunctshamt For simplicity, each field has a name: For shift instructions: “shift amount”

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10 R-Format Example MIPS Instruction: add $8,$9,$10 Binary number per field representation: Decimal number per field representation: hex representation: decimal representation: On Green Card: Format in column 1, opcodes in column 3 (Let’s look and then come back)

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11 M I P S Reference Data: CORE INSTRUCTION SET NAMEMNE- MON-IC FOR- MAT OPERATION (in Verilog) OPCODE/ FUNCT (hex) AddaddRR[rd] = R[rs] + R[rt] (1)0 / 20 hex Add ImmediateaddiIR[rt] = R[rs] + SignExtImm (1)(2) 8 hex Branch On Equal beqIif(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4 hex (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b’0}, immediate } (4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0} Later

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12 R-Format Instructions (REMINDER) Define “fields” of the following number of bits each: = opcodersrtrdfunctshamt For simplicity, each field has a name:

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13 R-Format Example MIPS Instruction: add $8,$9,$10 Binary number per field representation: Decimal number per field representation: Now let’s fill this in

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14 R-Format Example MIPS Instruction: add $8,$9,$ Binary number per field representation: Decimal number per field representation: hex representation: 012A 4020 hex decimal representation: 19,546,144 ten hex

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15 I-Format Instructions Define “fields” of the following number of bits each: = opcodersrtimmediate For simplicity, each field has a name: Let’s do an example using addi

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16 M I P S Reference Data: CORE INSTRUCTION SET NAMEMNE- MON-IC FOR- MAT OPERATION (in Verilog) OPCODE/ FUNCT (hex) AddaddRR[rd] = R[rs] + R[rt] (1)0 / 20 hex Add ImmediateaddiIR[rt] = R[rs] + SignExtImm (1)(2) 8 hex Branch On Equal beqIif(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4 hex (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b’0}, immediate } (4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}

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17 I-Format Example MIPS Instruction: addi $8,$9,7 Binary number per field representation: Decimal number per field representation:

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18 I-Format Example MIPS Instruction: addi $8,$9,7 Binary number per field representation: Decimal number per field representation: hex representation: 0x hex

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19 M I P S Reference Data: CORE INSTRUCTION SET NAMEMNE- MON-IC FOR- MAT OPERATION (in Verilog) OPCODE/ FUNCT (hex) AddaddRR[rd] = R[rs] + R[rt] (1)0 / 20 hex Add ImmediateaddiIR[rt] = R[rs] + SignExtImm (1)(2) 8 hex Branch On Equal beqIif(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4) 4 hex (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b’0}, immediate } (4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}

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20 addi $8,$9,7 Executing the addi instruction $8 $90x Suppose Immediate = 0x0007 (16 bits; 4 hex digits) SignExtImm = 0x (32 bits; 8 hex digits) A This will be more interesting when we get to negative numbers.

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21 Exercise Which instruction has same representation as 35 ten ? A. add $0, $0, $0 B. subu $s0,$s0,$s0 C. lw $0, 0($0) D. addi $0, $0, 35 E. subu $0, $0, $0 F. Trick question! Instructions are not numbers. Use Green Card to Answer

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22 Exercise Which instruction has same representation as 35 ten ? A. add $0, $0, $0 B. subu $s0,$s0,$s0 C. lw $0, 0($0) D. addi $0, $0, 35 E. subu $0, $0, $0 F. Trick question! Instructions are not numbers. Registers numbers and names: 0: $0, 8: $t0, 9:$t1, …,16: $s0, 17: $s1, …, Opcodes and function fields add : opcode = 0, function field = 32 subu : opcode = 0, function field = 35 addi : opcode = 8 lw : opcode =

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23 Which instruction bit pattern = number 35? A. add $0, $0, $0 B. subu $s0,$s0,$s0 C. lw $0, 0($0) D. addi $0, $0, 35 E. subu $0, $0, $0 F

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24 Logic Instructions Bit-wise logic operations Examples –and $t0, $s0, $s2# $t0 = $s0 ^ $s2 –or $s0, $t0, $t1# $s0 = $t0 | $t1 –nor $s0, $t0, $t1# $s0 = ~($t0 | $t1) –xor $s0, $t0, $t1# $s0 = $t0 ^ $t1 NameFieldsComments R-formatoprsrtrdshamtfunctLogic instruction format

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25 Logic Instructions: Example.text addi $t0,$0,0x32 addi $t1,$0,0x777 and $t2,$t1,$t0 $t0 $t1 $t2 Answer in class; also, replace and by or Next: andi and ori

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26 Andi and Ori andi I R[rt] & ZeroExtImm (3) lui I R[rt] = {immediate,16’b0} (3) ZeroExtImm = {16{1’b0},immediate} In Verilog: 4'b1001 // a 4-bit binary number 16'h704f // a 16-bit hex number 1b‘0 // a 1-bit binary number.text lui $t1,0x7F40 addi $t2,$t1,0x777 andi $t3,$t2,0x5555 In class

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27 Long Immediates (review) Sometimes we need a long immediate, e.g., 32 bits MIPS requires that we use two instructions –lui $t0, 0xaa55 Then we get lower-order 16 bits –ori $t0, $t0, 0xcc $t $t0

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28 Loading a memory address.data places values in memory starting at 0x So, 32 bits are needed to specify a memory address. Format I has a 16 bit field and Format J has a 26 bit field…neither is long enough. la $t0,0x is a pseudo instruction – not implemented in the hardware lui $1,4097 la $t0,0x ori $8,$1,8 lw $t1,0($t0)

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29 A program Get sample1.asm from the schedule Load it into the simulator Figure out the memory contents, labels Trace through the code

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30.data # sample1.asm a:.word 3,4 c:.word 5,6.text la $t0,c # address of c la $t1,k # address of k lw $s0,0($t0) # load c[0] lw $s1,4($t1) # load k[1] slt $s3,$s0,$s1 # if c[0] < k[1], $s3 = 1, else $s3 = 0 beq $s3,$0,notless # if c[0] < k[1] swap their values sw $s0,4($t1) sw $s1,0($t0) notless:.data k:.word 0xf,0x11,0x12

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