# Princess Sumaya University

## Presentation on theme: "Princess Sumaya University"— Presentation transcript:

Princess Sumaya University د. بســام كحـالــه Dr. Bassam Kahhaleh
Digital Logic Design 22343 Computer Organization & Design د. بســام كحـالــه Dr. Bassam Kahhaleh Dr. Bassam Kahhaleh

Princess Sumaya University
Digital Logic Design Computer Organization & Design Chapter 2: Instructions: Language of the Computer Dr. Bassam Kahhaleh

Basic Computer Organization
The 5 Classic Components of a Computer The Basic Hardware/Software Interface The Stored-Program Concept 9:51 AM

Assembly Language Instruction:
Instructions Assembly Language Instruction: Perform: a = b + c ADD a, b, c ; a  b + c What are ‘a’, ‘b’ and ‘c’? The storage concept: Registers (R1, R2 …) Memory Sequence of Instructions: Perform: a = (b + c) – (d + e) 9:51 AM

Design Principle 1: Simplicity Favors Regularity
Instructions Design Principle 1: Simplicity Favors Regularity Fixed number of operands Arithmetic operations on registers only Design Principle 2: Smaller is Faster Small number of registers  faster hardware Fill registers with data Not enough registers to hold all data Simpler hardware 9:51 AM

Data Transfer Instructions
Memory Operands Data Transfer Instructions Memory Address (Location) Slower than registers Lower bandwidth than registers Keep commonly used data in registers and avoid Spilling Registers. Load and Store Instructions 1 2 Memory 9:51 AM

Design Principle 3: Make the Common Case Fast
Operands Design Principle 3: Make the Common Case Fast Constant operands: Perform a = b + 4 Immediate operands Memory b 4 21 22 9:51 AM

Memory Access Height and Width Address & Data Read & Write 1 KB 4 KB
16 Locations  1 K Locations  1 M Locations  Read & Write 1024 8 bit 1 KB Memory 4301 0001 21 22 9:51 AM

Stored Program Architecture
Memory 1024 x 32 Instructions (Program) Opcode Operands Operands (Data) Binary Operand 9:51 AM

Memory Organization Byte Access Word Access • 20 Byte 21 Byte •
20 Byte Byte Byte Byte 24 Byte Byte Byte Byte 9:51 AM

Memory Organization Mixed Access Little Indian Odd/Even Alignment DATA
20 Byte Byte 22 Byte Byte MSB DATA BUS LSB 9:51 AM

Memory Organization Mixed Access Alignment! DATA BUS •
20 Byte Byte Byte Byte 24 Byte Byte Byte Byte MSB DATA BUS LSB 9:51 AM

Instruction Representation
Instruction Format Machine Language & Machine Code Sequence of instructions Design Principle 4: Good Design Demands Good Compromises Assembly Language Opcode Operands ADD R1, R2, F 0101 0001 0010 F Machine Language 9:51 AM

Operations (Opcodes) Arithmetic Logic 1 0 1 0 0 1 1 1
Add, Sub, Mul, Div, Inc, Dec … Logic Shift Logical & Arithmetic Right & Left Bitwise AND, OR, XOR Complement (NOT) 9:51 AM

Shift Operation for Multiplication
Operations (Opcodes) Shift Operation for Multiplication Multiply by 2 Shift Left 1 bit Unsigned Binary 2’s Complement Multiply by 10 BCD Shift Left 4 bits 9:51 AM

Making Decisions (Conditional Branches)
Control Instructions Making Decisions (Conditional Branches) Perform if (i == j) then a = b + c else a = b – c i == j ? a = b + c a = b – c 9:51 AM

Transferring Execution
Control Instructions Transferring Execution Unconditional Branch or Jump Call Subroutine Software Interrupt 9:51 AM

Intel Architecture IA-32
Year Microprocessor Address Bits Data Bits Transistors 1971 4004 12 4 2,300 1974 8080 16 8 6,000 1978 8086 20 16/8 29,000 1982 80286 24 134,000 1985 80386 32 32/16/8 275,000 1989 80486 1,200,000 1992 Pentium 3,100,000 1995 Pentium Pro 5,500,000 1997 Pentium II 7,500,000 1999 Pentium III 9,500,000 2001 Pentium 4 42,000,000 2004 Pentium 4 EM64T 64 125,000,000 2008 Core 2 Quad 820,000,000 9:51 AM

Intel Architecture IA-32
General-Purpose Registers (GPRs) Segment Registers Segmented Memory Addressing (Real Mode) Also: “Accumulator” EAX EAX AX AL AX AL “Base” EBX BX BL “Count” ECX CX CL “Division” EDX DX DL “String Source” ESI SI “String Destination” EDI DI CS SS DS 9:51 AM

Intel Architecture IA-32
Variable Length Instruction Format 9:51 AM

Chapter 2 The End