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©UCB CPSC 161 Lecture 3 Prof. L.N. Bhuyan
©UCB °simple instructions all 32 bits wide °very structured, no unnecessary baggage °only three instruction formats op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ Review of MIPS Instruction Formats
©UCB MIPS Instructions: R-format I- format <- R-format <- J-format <- R-format <- J-format
©UCB Assembly Operands: Registers °Naming of 32 MIPS registers: instead of r0, r1, …, r31, use $s0, $s1, … for registers corresponding to C variables $t0, $t1, … for registers corresponding to temporary variables Will explain mapping convention later of $s0, $s1, …, $t0, $t1, …, to r0, r1, … °Note: whereas C declares its variables (e.g., int fahr ), Assembly operands (registers) are fixed and not declared
©UCB Policy of Use Conventions
©UCB Role of Registers vs. Memory °What if more variables than registers? Compiler tries to keep most frequently used variables in registers Writing less common to memory: spilling °Why not keep all variables in memory? Smaller is faster: registers are faster than memory Registers more versatile: -MIPS arithmetic instruction can read 2, operate on them, and write 1 per instruction -MIPS data transfer only read or write 1 operand per instruction, and no operation
©UCB Compilation using Registers °Compile by hand using registers: f = (g + h) - (i + j); Register Allocations: f: $s0, g: $s1, h: $s2, i: $s3, j: $s4 °MIPS Instructions: add $s0,$s1,$s2# $s0 = g+h add $t1,$s3,$s4# $t1 = i+j sub $s0,$s0,$t1# f=(g+h)-(i+j)
©UCB MIPS Instruction Encoding Examples of some Opcodes: Instruction Format Opcode shamt funct Add R Sub R Shift (by 4) R Add (imm) I 8 n.a n.a Lw (load word) I 35 n.a n.a Sw (store word) I 43 n.a n.a
©UCB Data Transfer Instruction: Memory to Reg °Load: moves data from memory to register Syntax: 1) operation name 2) register to be loaded 3) constant and register to access memory °MIPS name, lw for load word: Example: lw $t0, 8($s3) Called “offset” Called “base register” or “base address register” or “base address”
©UCB Compilation when Operand is in Memory Q: Compile by hand using registers: g = h + A; g:$s1, h:$s2, $ s3 :starting (base) address of array A °Since A is in memory, 1st transfer from memory to (temporary) register: lw$t0,300($s3) # Adds 300 to $s3 to select A, puts into $t0 lw $t0,1200($s3) # For byte addressable machines 300x4 °Next add it to h and place in g add $s1,$s2,$t0 # $s1= h+A HW: Compile A = h + A
©UCB Tanslating to MIPS Machine Language °From the instruction set, Opcode for Lw is 35. Opcode for add is 0 with funct 32. °From register assignment table, t0=8, s1=17, s2=18 and s3=19. °Instruction consists of op=5 bits, rs=5bits, rt=5bits, rd=5bits, shamt=5bits and funct=6bits for R format and address=16 bits instead of rd,shamt and funct for I format: total=32 bits Assembly language lw $t0, 1200($s3) and add $s1,$s2,$t0 translate to: op | rs | rt | rd | address/shamt | funct | 35 | 19 | 8 | 1200 | 0 | 18 | 8 | 17 | 0 | 32 |
©UCB Compile with variable index °What if array index not a constant? g = h + A[i]; g:$s1, h:$s2, i:$s4, $s3 :base address of A °To load A[i] into a register, first turn i into a byte address; multiply by 4 °How multiply using adds? i + i = 2i, 2i + 2i = 4i add $t1,$s4,$s4# $t1 = 2*i add $t1,$t1,$t1# $t1 = 4*i
©UCB Compile with variable index, con’t °Next add to base of A: add $t1,$t1,$s3 #$t1=address of #A[i] (4*i+$s3) °Now load A[i] into a temporary register: lw $t0,0($t1) # Temp $t0 = A[i] °Finally add to h and put sum in g : add $s1,$s2,$t0 # g = h + A[i]
©UCB MIPS arithmetic instructions InstructionExampleMeaningComments add add $1,$2,$3$1 = $2 + $33 operands; subtractsub $1,$2,$3$1 = $2 – $33 operands; add immediateaddi $1,$2,100$1 = $ constant; add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands; add imm. unsign.addiu $1,$2,100$1 = $ constant; multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product multiply unsignedmultu$2,$3Hi, Lo = $2 x $364-bit unsigned product divide div $2,$3Lo = $2 ÷ $3,Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3Lo = $2 ÷ $3,Unsigned quotient & remainder Hi = $2 mod $3 Move from Himfhi $1$1 = HiUsed to get copy of Hi Move from Lomflo $1$1 = LoUsed to get copy of Lo Which add for address arithmetic? Which add for integers?
©UCB MIPS logical instructions InstructionExampleMeaningComment and and $1,$2,$3$1 = $2 & $33 reg. operands; Logical AND oror $1,$2,$3$1 = $2 | $33 reg. operands; Logical OR xorxor $1,$2,$3$1 = $2 $33 reg. operands; Logical XOR nornor $1,$2,$3$1 = ~($2 |$3)3 reg. operands; Logical NOR and immediateandi $1,$2,10$1 = $2 & 10Logical AND reg, constant or immediateori $1,$2,10$1 = $2 | 10Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10Logical XOR reg, constant shift left logicalsll $1,$2,10$1 = $2 << 10Shift left by constant shift right logicalsrl $1,$2,10$1 = $2 >> 10Shift right by constant shift right arithm.sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) shift left logicalsllv $1,$2,$3$1 = $2 << $3 Shift left by variable shift right logicalsrlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm.srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable
©UCB MIPS data transfer instructions InstructionComment SW 500(R4), R3Store word SH 502(R2), R3Store half SB 41(R3), R2Store byte LW R1, 30(R2)Load word LH R1, 40(R3)Load halfword LHU R1, 40(R3)Load halfword unsigned LB R1, 40(R3)Load byte LBU R1, 40(R3)Load byte unsigned LUI R1, 40Load Upper Immediate (16 bits shifted left by 16) 0000 … 0000 LUI R5 R5
©UCB Section 2.6 MIPS decision instructions °Decision instruction in MIPS: beq register1, register2, L1 beq is “Branch if (registers are) equal” Same meaning as (using C): if (register1==register2) go to L1 °Complementary MIPS decision instruction bne register1, register2, L1 bne is “Branch if (registers are) not equal” Same meaning as (using C): if (register1!=register2) go to L1 °Called conditional branches
©UCB Compiling C if into MIPS: Summary °Compile by hand if (i == j) f=g+h; else f=g-h; Mapping f : $s0, g : $s1, h : $s2, i : $s3, j : $s4 beq $s3,s4, True # branch i==j sub $s0,$s1,$s2 # f=g-h(false) j Exit # go to Exit True: add $s0,$s1,$s2 # f=g+h (true) Exit: °Note: Compiler supplies labels, branches not found in HLL code; often it flips the condition to branch to false part i == j? f=g+hf=g-h (false) i != j (true) i == j C MIPSMIPS
©UCB Loops in C/Assembly: Summary Loop:g = g + A[i]; i = i + j; if (i != h) goto Loop; ( g, h, i, j :$s1,$s2,$s3,$s4 : base of A :$s5) Loop: add $t1,$s3,$s3 #$t1= 2*i add $t1,$t1,$t1 #$t1= 4*i add $t1,$t1,$s5 #$t1=addr A lw $t1,0($t1) #$t1=A[i] add $s1,$s1,$t1 #g=g+A[i] add $s3,$s3,$s4 #i=i + j bne $s3,$s2,Loop# goto Loop # if i!=h C MIPSMIPS
©UCB Branch Addressing: PC-relative °Conditional Branch: beq $t0,$t1,label address just 16 bits (2 16 ), program too small! °Option: always add address to a register PC = Register + Branch address Change register contents => bigger programs °Which register? How use conditional branch? if-else, loops Near current instruction => use PC as reg! PC-relative addressing (PC+4) +/ words oprsrtaddress 6 bits 5 bits 16 bits I
©UCB Branch Addressing: Jumps, J format °j label # go to label j has only one operand; add format large address allows large programs bright idea: address of instruction always multiple of 4 (instructions always words) => store number of word, save 2 bits Example: j exit # exit = PC = address * 4 + upper 4 bits of old PC bits26 bits opaddress J J
©UCB Branch Addressing: PC-relative Example Loop:slt$t1,$zero,$a1# t1=9,a1=5 beq$t1,$zero,Exit# no=>Exit add$t0,$t0,$a0# t0=8,a0=4 subi$a1,$a1,1# a1=5 j Loop# goto Loop Exit:add $v0,$t0,$zero# v0=2,t0= Address = *4 Set t1=1 if $zero < $a1
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