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Optimization of Sequential Networks Step in Synthesis: Problem Flow Table Reduce States Minimum-State Table State Assignment Circuit Transition Table Flip-Flop.

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Presentation on theme: "Optimization of Sequential Networks Step in Synthesis: Problem Flow Table Reduce States Minimum-State Table State Assignment Circuit Transition Table Flip-Flop."— Presentation transcript:

1 Optimization of Sequential Networks Step in Synthesis: Problem Flow Table Reduce States Minimum-State Table State Assignment Circuit Transition Table Flip-Flop or Latch Selection Excitation Table or Functions We focus here on minimizing states for: 1.Completely Specified Sequential Machines – specified by flow tables with no don’t cares 2.Incompletely Specified Sequential Machines – specified by flow tables with don’t cares

2 State Reduction Goal Given a flow table, to find an indistinguishable, minimum- state flow table. Note: this leads to a circuit with fewest possible memory elements & usually a minimum cost (but not always) Indistinguishable Flow Tables - flow tables that specify identical output sequences for the same input sequence. Inaccessible States – states not reached from initial state or from desired pattern We want to eliminate inaccessible states by state reduction or by making them accessible. We assume this is done before other state reduction techniques are employed.

3 Table Reduction for Completely Specified Networks Present state Next state, output x=0x=1 AB,1C,0 BB,1C,0 CA,0D,1 DA,0D,1 Present state Next state, output x=0x=1 EE,1F,0 FE,0F,1 Consider two flow tables: Table TTable T* If the same input sequence is applied to T or T*, they produce the same output sequences Example: for sequence x = 011, z(T,A)=101, z(T*,E)=101

4 Distinguishability Two states of a FSM s i and s j are distinguishable if they produce different output sequences for the same input sequence. Such an input sequence is a distinguishing sequence of ( s i, s j ) Two states of a FSM s i and s j are equivalent or indistinguishable if they produce the same output sequences for the same input sequence and are members of an indistinguishable class. If there is a distinguishing sequence with length k for ( s i, s j ), the ( s i, s j ) is k -distinguishable Goal: to merge all equivalent states to obtain the minimum number of states.

5 Partition and Array Techniques to Produce Minimum-State Tables Partition Test Steps: 1.Class States by output only Present state Next state, output x=0x=1 Q0Q0 Q 2,0Q 1,1 Q1Q1 Q 2,1Q 0,1 Q2Q2 Q 4,0Q 1,1 Q3Q3 Q 5,0Q 0,0 Q4Q4 Q 6,1 Q5Q5 Q3, 1Q3, 1Q 2,1 Q6Q6 Q 4,1Q 2,1 Present state Next state, output x=0x=1 Q 0 AQ 2 A,0Q 1 B,1 Q 1 BQ 2 A,1Q 0 A,1 Q 2 AQ 4 A,0Q 1 B,1 Q 3 CQ 5 B,0Q 0 A,0 Q 4 AQ 0 A,0Q 6 B,1 Q 5 BQ 3 C, 1Q 2 A,1 Q 6 BQ 4 A,1Q 2 A,1 A[Q 0 Q 2 Q 4 ] B[Q 1 Q 5 Q 6 ] C[Q 3 ]

6 Partition Test Steps: 2.Check Next States within classes, if necessary further subclass Present state Next state, output x=0x=1 Q 0 AQ 2 A,0Q 1 B,1 Q 1 BQ 2 A,1Q 0 A,1 Q 2 AQ 4 A,0Q 1 B,1 Q 3 CQ 5 BD,0Q 0 A,0 Q 4 AQ 0 A,0Q 6 B,1 Q 5 BDQ 3 C, 1Q 2 A,1 Q 6 BQ 4 A,1Q 2 A,1 A[Q 0 Q 2 Q 4 ] B[Q 1 Q 6 ] BD[Q 5 ] C[Q 3 ]

7 Partition Test Steps: 3. Minimum-State Table is set of indistinguishable classes. Present state Next state, output x=0x=1 Q 0 AQ 2 A,0Q 1 B,1 Q 1 BQ 2 A,1Q 0 A,1 Q 3 CQ 5 BD,0Q 0 A,0 Q 5 BDQ 3 C, 1Q 2 A,1 A[Q 0 Q 2 Q 4 ] B[Q 1 Q 6 ] BD[Q 5 ] C[Q 3 ]

8 Array Technique Steps: 1.Form Pair Chart with ½(S)(S-1) entries. Place X in cells that correspond to state pairs having different outputs. Present state Next state, output x=0x=1 Q0Q0 Q 2,0Q 1,1 Q1Q1 Q 2,1Q 0,1 Q2Q2 Q 4,0Q 1,1 Q3Q3 Q 5,0Q 0,0 Q4Q4 Q 6,1 Q5Q5 Q3, 1Q3, 1Q 2,1 Q6Q6 Q 4,1Q 2,1 X X X Q2Q4Q2Q4 X X X X X X X X X X X X Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q0Q0 Q0Q2Q1Q6Q0Q2Q1Q6 Q2Q3Q0Q2Q2Q3Q0Q2 Q2Q4Q0Q2Q2Q4Q0Q2 Q1Q6Q0Q4Q1Q6Q0Q4 Q3Q4Q3Q4 2. Each remaining pair examined, place asterisk in cells with identical next state entries. Place pairs of states that must be indistinguishable in order that pair represented by cell be indistinguishable

9 Array Technique X X X Q2Q4Q2Q4 X X X X X X X X X X X X Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q0Q0 Q0Q2Q1Q6Q0Q2Q1Q6 Q2Q3Q0Q2Q2Q3Q0Q2 Q2Q4Q0Q2Q2Q4Q0Q2 Q1Q6Q0Q4Q1Q6Q0Q4 Q3Q4Q3Q4 3. Make successive passes through array Xing out cells having pair entries that are distinguishable (marked by X elsewhere in Table) Result: [Q 0 Q 2 Q 4 ] [Q 1 Q 6 ] ] [Q 3 ] [Q 5 ]

10 Optimization of Incompletely Specified Machines Some definitions: Two states are I-Equivalent IFF 1.Outputs are identical, if specified 2.Matching d-outputs occur 3.Matching unspecified next states occur or specified next states must be equivalent. Two states are Compatible IFF 1.Outputs are identical, if specified 2.Compatible next-states occur, if both are specified. Maximal Compatible Classes - classes that are not subsets of any other compatibility class.

11 Optimization of Incompletely Specified Machines Flow TableI-Equivalent States Removed Compatible State Pair Chart Maximal Compatibility Classes Minimum-State Table

12 Optimization of Incompletely Specified Machines Steps in finding Reduced Table: 1.Remove I-Equivalence states 2.Find Maximal Compatibility Classes 3.Form Flow Table in which each state corresponds to a maximal compatibility class subject to satisfying the closure property and all states of the original table are represented, that is satisfying the covering property.

13 Optimization of Incompletely Specified Machines – Array Technique Example: Present state Next state, output I1I1 I2I2 I3I3 I4I4 A--E,1- BC,0A,1B,0- CC,0D,1-A,0 D-E,1B,-- EB,0-C,-B,0 BE * X BC AE AD BC DE B C D E BCDA AB. BC CE Compatibility State Set: [AC], [AD], [CD], [ACD], [BC], [BE], [ED] Maximal compatibility classes

14 Optimization of Incompletely Specified Machines – Merger Graph Example: Present state Next state, output I1I1 I2I2 I3I3 I4I4 A--E,1- BC,0A,1B,0- CC,0D,1-A,0 D-E,1B,-- EB,0-C,-B,0 Compatibility State Set: [AC], [AD], [CD], [ACD], [BC], [BE], [ED] Maximal compatibility classes A E D C B (DE) (BE) (BC) (AD) (AE) (BC) (DE) (BC) (AB) Complete Subgraph

15 State Compatibility Graph State Compatibility Graph is a directed graph satisfying the conditions: 1.Each node corresponds to a compatible state set. 2.When a state set implies another state set S, attach OR directed edges from the nodes corresponding to the original state set to the node corresponding to the state sets containing S. 3. When a state set implies two or more state sets: S 0, …., S k-1, S k, Attach AND directed edges from the node corresponding to the original state set to the nodes that correspond to S 0, …., S k-1, S k

16 Finding Minimum Number of States Using State Compatibility Graph Must Satisfy Two Conditions: 1.Covering Property – Each state of the FSM is contained by at least one compatible set V 2.Closure Property: If v i  V, then V i  V, where V i is the set of implied compatible sets. V i satisfies the following condition: for the OR directed edges that emerge from v i, V i contains the nodes for at least one edge. For the AND directed edges that emerge from v i, V i contains the nodes for all the AND directed edges.

17 Addressing the Closure Property V 1 : [BE] V 2 : [AD] V 3 : [CD] V 4 : [BC] V 5 : [ACD] V 6 : [DE] V 7 : [AC] V 8 : [A] V 9 : [B] V 10 : [C] V 11 : [D] V 12 : [E] V1V1 V 7 V 8 V 9 V 10 V 11 V 12 V4V4 V3V3 V6V6 V5V5 V2V2 AND OR Present state Next state, output I1I1 I2I2 I3I3 I4I4 A--E,1- BC,0A,1B,0- CC,0D,1-A,0 D-E,1B,-- EB,0-C,-B,0 E D B (DE) (BE) (BC) (AD) (AE) (BC) (DE) (BC) (AB)

18 Optimization Example Covering Property State A: v 2 + v 5 + v 7 + v 8 = 1 State B: v 1 + v 4 + v 9 = 1 State C: v 3 + v 4 + v 5 + v 7 + v 10 = 1 State D: v 2 + v 3 + v 5 + v 6 + v 11 = 1 State E: v 1 + v 6 + v 12 = 1

19 Closure Property Example From the state compatibility graph v 1  v 4, so v 1 + v 4 = 1 v 2  v 1, so v 2 + v 1 = 1 v 3  v 6, so v 3 + v 6 = 1 v 4  (v 2 + v 5 ), so v 4 + v 2 + v 5 = 1 v 5  v 1 v 6, so (v 5 + v 1 )(v 5 + v 6 ) = 1 v 6  v 4, so v 6 + v 4 = 1 AND of all conditions gives solution of minimum weight

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