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Sequential Circuit Synthesis - II Virendra Singh Indian Institute of Science Bangalore IEP on Digital System Synthesis, IIT Kanpur.

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Presentation on theme: "Sequential Circuit Synthesis - II Virendra Singh Indian Institute of Science Bangalore IEP on Digital System Synthesis, IIT Kanpur."— Presentation transcript:

1 Sequential Circuit Synthesis - II Virendra Singh Indian Institute of Science Bangalore IEP on Digital System Synthesis, IIT Kanpur

2 Dec 14, Incompletely Specified Machine PSNS, z X = 0X = 1 AB, 1--, -- B--, 0C, 0 CA, 1B, 0  The specified behaviour of a machine with partially specified transitions can be described by another machine whose state transitions are completely specified  The transformation is accomplished by replacing all the dashes in the next state entries by T and adding a terminal state T whose output are unspecified PSNS, z X = 0X = 1 AB, 1T, -- BT, 0C, 0 CA, 1B, 0 TT, --

3 Dec 14, State S i of M1 is said to cover, or contain, state S j of M2 if and only if every input sequence applicable to S j is also applicable to S i, and its application to both M1 and M2 when they are initially in S i and S j, respectively, results in identical output sequences whenever the outputs of M2 are specified Machine M1 is said to cover machine M2 if and only if, for every state S j in M2, there is a corresponding state S i in M1 s.t. S i covers S j Compatible States

4 Dec 14, Two states S i and S j of machine M are compatible, if and only if, for every input sequence applicable to to both S i and S j, the same output sequence will be produced whenever both outputs are specified and regardless of whether S i or S j is the initial state S i and S j are compatible, if and only if, their outputs are not conflicting (i.e., identical when specified) and their I i -successor, for every I i for which both are specified, are the same or also compatible. A set of states (S i, S j, S k, ….) is called compatible if all its members are compatible Compatible States

5 Dec 14, A compatible Ci is said to be larger than, or to cover, another compatible Cj, if and only if, every state in Cj is also contained in Ci A compatible is maximal if it is not covered by any other compatible Compatible States

6 Dec 14, PSNS, z X = 0X= 1 AC, 1E, -- BC, --E, 1 CB, 0A, 1 DD, 0E, 1 ED, 1A, 0 PSNS, z X = 0X=1 AC, 1E, 1 CB, 0A, 1 DD, 0E, 1 ED, 1A, 0 Compatible States PSNS, z X= 0X=1 AE - αβ, 1α, 0 BCD - ββ, 0α, 1

7 Dec 14, A set of states is compatible if and only if every pair of the states in that set is compatible PSNS, z X = 0X=1 AA, 0C, 0 BB, 0B, -- CB, 0A, 1 Compatible States PSNS, z X = 0X=1 AA, 0C, 0 B’B’, 0B’’, -- B’’B+, 0B’, 1 CB+, 0A, 1

8 Dec 14, PSNS, z X= 0X=1 (AB’) – αα, 0β, 0 (B”C) – βα, 0α, 1 Compatible States PSNS, z X= 0X=1 (AB’) – αα, 0β, 0 (B’’C) - ββ, 0α, 1 B+ = B’ B+ = B”

9 Dec 14, Merger Graph PSNS, z I1I2I3I4 A---C, 1E, 1B, 1 BE, 0--- CF, 0F, 1--- D B, 1--- E F, 0A, 0D, 1 FC, 0---B, 0C, 1 Transforming into fully specified machine may not be optimal one First generate the entire set of compatibles Select an appropriate subset, which will form the basis of state reduction leading to minimum machine

10 Dec 14, Merger Graph A set of states is compatible if and only if every pair of states in that set is compatible It is sufficient to consider pair of states and use them to generate entire set Compatible pair of states is referred as compatible pairs Let the Ik-successors of Si and Sj be Sp and Sq, respectively; then (Sp Sq) said to be implied by (SiSj) (SpSq) are referred as implied pair

11 Dec 14, Merger Graph Merger graph is undirected graph 1.It consists of n-vertices, each of which corresponds to a state of M 2.For each pair of states (Si Sj) in M whose next state and output entries are not conflicting, an undirected arc is drawn between vertices Si and Sj 3.If for a pair of states (Si Sj) the corresponding outputs under all inputs are not conflicting, but successors are not the same, an interrupted arc is drawn between Si and Sj, and then implied pairs are entered in the space

12 Dec 14, Merger Graph PSNS, z I1I2I3I4 A---C, 1E, 1B, 1 BE, 0--- CF, 0F, 1--- D B, 1--- E F, 0A, 0D, 1 FC, 0---B, 0C, 1 A C B D E F (AB) (CD) (BE) (EF) (CF)

13 Dec 14, Merger Graph Merger graph is undirected graph Nine compatible pairs (AB), (AC), (AD), (BC), (BD), (BE), (CD), (CF), (EF) (AB), (AC), (BC) are compatible => (ABC) compatible Find minimal set of compatible {(ABCD), (BC), (BE), (DE)}

14 Dec 14, Merger Graph  A set of compatible (for machine M) is said to be closed if, for every compatible contained in the set, all its implied also contained in the set.  A closed set of compatibles which contains all the sates of M is called closed covering  A set {(AD), (BE), (CD)} is a closed covering PSNS, z I1I2I3I4 (AB) - αδ, 0β, 1δ, 1α, 1 (CD) - βδ, 0δ, 1α, 1--- (EF) - δβ, 0δ, 0α, 0Β, 0

15 Dec 14, Compatible Graph  The compatible graph is a directed graph whose vertices corresponding to all compatible pairs, and arc leads from vertex (Si Sj) to vertex (Sp Sq) if and only if (Si Sj) implies (Sp Sq)  It is a tool which aids in the search for a minimal closed covering  Compatible pairs are obtained from merger graph

16 Dec 14, Compatibility Graph PSNS, z I1I2I3I4 A--- E, 1--- BC, 0A, 1B, 0--- CC, 0D, 1---A, 0 D---E, 1B, EB, 0---C, --B, 0 A B C D E (BC) (AB) (BC) (AE) (CF) (DE) (AD) (BE) Merger Graph

17 Dec 14, Compatibility Graph A B C D E (BC) (AB) (BC) (AE) (CF) (DE) (AD) (BE) Merger Graph AC AD BC DE CD BE

18 Dec 14, Minimization using Network Model  Behaviour of sequential circuit can be described by traces, i.e., sequence of inputs and outputs  Various approaches to optimize  Ignore registers and optimize the combinational logic  Retiming – move position of registers only

19 Dec 14, Retiming  Minimize cycle time or the area of synchronous circuits by changing the position of the registers  Cycle time is bounded from below by the critical path delay in the combinational circuit  Retiming aims at placing the registers in the appropriate position, so that the critical paths they embrace are as short as possible  Moving registers may increase or decrease the number of regsisters

20 Dec 14, Retiming + Host δ + δ + δδ

21 Dec 14,

22 Dec 14,

23 Dec 14, Example Machine M2 PSNS, z X = 0X = 1 AE, 0C, 0 B A, 0 CB, 0G, 0 D A, 0 EF, 1B, 0 FE, 0D, 0 G G, 0 P0 = (ABCDEFG) P1 = (ABCDFG) (E) P2 = (AF) (BCDG) (E) P3 = (AF) (BD) (CG) (E) P4 = (A) (F) (BD) (CG) (E) P5 = (A) (F) (BD) (CG) (E)


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