Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 2 Virtual Storage System Fulfill the main memory capacity needs, not to fill the speed gap between processor and memory Thus, it is a software system Virtual address space >> Physical address space Needs translation of the virtual addresses to the physical addresses –Page Table –Usually entire Page Table can not be loaded in the memory Very slow translation Address translation should be fast - Shouldn’t need more than 1 memory access for the fast translation –TLB made of associative memory –Cache
Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 3 Virtual Memory Virtual address (2 32, 2 64 ) to Physical Address mapping (2 28 ) Virtual memory terms of cache terms: –Cache block? - page or segment –Cache Miss? - page fault or address fault How is virtual memory different from caches? –What Controls Replacement - HW and SW –Size (transfer unit, mapping mechanisms) –Lower level use - secondary storage ( magnetic disk)
Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 4 Typical Ranges Of Parameters Block(page) size16-128 bytes4KB - 64KB Hit time1-2 clock cycles40-100 clock cycles Miss penalty8- 100 clock cycles700,000-6,000,000 (Access time)(6-60 clock cycles)(500,000- 4,000,000) (Transfer time)(2-40 clcok cycles)(200,000- 2,000,000) Miss rate0.5-10%0.00001 - 0.001% Data memory size0.016-1MB16-8192MB ParameterFirst-level cacheVirtual memory
Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 5 Virtual Storage 4Qs for Virtual Memory? –Q1: Where can a block be placed in the upper level? Fully Associative, Set Associative, Direct Mapped –Q2: How is a block found if it is in the upper level? Tag/Block page table, multi-level page table, inverted page table, translation look-aside buffer (TLB) –Q3: Which block should be replaced on a miss? Random, LRU –Q4: What happens on a write? Write Back or Write Through (with Write Buffer)
Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 6 Fast Translation: Translation Buffer 1 2 3 4 Cache of translated addresses Alpha 21064 TLB: 32 entry fully associative... Page-frame Address Page Offset V R W Tag Physical Addr 32:1 MUX Low order 13 bits of Address High order 21 bits of address 34-bit Physical Address TLB...
Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 7 Selecting the Page Size Reasons for larger page size –Page table size is inversely proportional to the page size; memory can be saved with larger page, i.e. with smaller PT –Fast cache hit time, easy when cache page size (VA caches); bigger page is feasible as cache size grows –Transferring larger pages to or from secondary storage, possibly over a network, is more efficient –Number of TLB entries are restricted by clock cycle time, so a larger page size maps more memory, thereby reducing TLB misses Reasons for a smaller page size –Fragmentation: don’t waste storage; data must be contiguous within page –Quicker process start for small pages(??) Hybrid solution: multiple page sizes –Alpha: 8KB, 16KB, 32 KB, 64 KB pages (43, 47, 51, 55 virt addr bits)
Virtual Storage SystemCS510 Computer ArchitecturesLecture 14 - 8 Alpha VM Mapping “64-bit” address divided into 3 segments –seg0 (bit 63=0): user code/heap –seg1 (bit 63 = 1, 62 = 1): user stack –kseg (bit 63 = 1, 62 = 0): kernel segment for OS Seg0/Seg1 000 … 0 or selector 111 … 1 Level1 Level2 Level3 Page Offset 21 10 10 10 13 + L1 Page Tbl + + L2 Page Tbl L3 Page Tbl Physical Page-frame No. Page Offset Main Memory Address Virtual Address Physical Address 8 bytes 32-bit address 32 bits fields Page Table Base Register Three-level page table, each fits in one page Alpha: only 43 unique bits of VA (future min page size up to 64KB => 55 bits of VA) PTE bits; valid, kernel & user read & write enable (No reference, use, or dirty bit)