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Virtual Memory Really this is in OS – but We need to see how the OS will interact with the HW Peer Instruction Lecture Materials for Computer Architecture.

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Presentation on theme: "Virtual Memory Really this is in OS – but We need to see how the OS will interact with the HW Peer Instruction Lecture Materials for Computer Architecture."— Presentation transcript:

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2 Virtual Memory Really this is in OS – but We need to see how the OS will interact with the HW Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Dr. Leo Porter Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License Read 4.10

3 Virtual Memory It’s just another level in the cache/memory hierarchy Virtual memory is the name of the technique that allows us to view main memory as a cache of a larger memory space (on disk). cpu $ cache memory disk cacheing virtual memory Add latencies 1-4 (L2 – 14) ,000,000-80,000,000

4 Virtual Memory What happens if another program in the processor uses the same addresses that yours does? What happens if your program uses addresses that don’t exist in the machine? What happens to “holes” in the address space your program uses? Can someone else’s program touch your data (or vice versa)?

5 Virtual Memory is just a mapping function from virtual memory addresses to physical memory locations, which allows cacheing of virtual pages in physical memory. Required because main memory is fully associative. Virtual Page Number A zero valid bit means…

6 Virtual Memory mapping physical addresses virtual addresses disk

7 Address translation via the page table virtual page numberpage offset valid physical page number page table reg physical page numberpage offset virtual address physical address page table all page mappings are in the page table, so hit/miss is determined solely by the valid bit (i.e., no tag)

8 Virtual Memory Suppose you have 8 KB pages, a 64 bit byte address, and 512MB of RAM. How many bits are translated (from your virtual page number to your physical page number)? SelectionVirtual Page #Physical Page # A5116 B1916 C5129 D1929 ENone of the above

9 Address translation via the page table virtual page numberpage offset valid physical page number page table reg physical page numberpage offset virtual address physical address page table 8 KB pages, a 64 bit byte address, and 512MB of RAM

10 Virtual Memory So far – given what we know about VM, what is the fewest number of accesses to main memory possibly from a single MIPS lw instruction? Write – NO TLB I Page Table lookup I Miss D Page Table Lookup D Miss SelectionCache Miss A0 B1 C2 D3 E3+

11 Making Address Translation Fast A cache for address translations: translation lookaside buffer (TLB) A zero valid bit means…

12 TLBs and caches Block

13 32-bit virtual addresses, 8 KB pages, 2 GB of RAM. Your cache has 64 byte blocks and is 32 KB in size. You are considering 2-way or 4- way. Your boss says 4-way would have a better hit time – is he right? SelectionRight?Reason AYes4-way caches always have better hit times BYesThis 4-way cache could do more in parallel than a 2-way cache CNo2-way caches always have better hit times DNoThis 2-way cache could do more in parallel than a 4-way cache ENoA different reason from above

14 TLBs and caches Block 8KB page, 2 GB RAM, 2-way vs. 4way 64 byte blocks, 32KB 8KB = 2^13 32KB = 2^15

15 Walkthrough the FIRST memory access TLB Miss TLB exception Fill TLB Page fault Call OS to replace the page and update page table Fill TLB with now valid entry Request that physical address Cache miss Memory hit Fill

16 Walkthrough a COMMON memory access TLB hit/translate Cache hit These could potentially Be in parallel

17 Virtual Memory – Real Examples OS+Presenter+misc > 650MB 512MB of RAM Mention WoW example

18 Virtual Memory Key Points How does virtual memory provide: –protection? –sharing? –performance? –illusion of large main memory? Virtual Memory requires twice as many memory accesses, so we cache page table entries in the TLB. Three things can go wrong on a memory access: cache miss, TLB miss, page fault.


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