Download presentation

Presentation is loading. Please wait.

Published byDrew Beecroft Modified over 3 years ago

1
EE105 Fall 2007Lecture 13, Slide 1Prof. Liu, UC Berkeley Lecture 13 OUTLINE Cascode Stage: final comments Frequency Response – General considerations – High-frequency BJT model – Miller’s Theorem – Frequency response of CE stage Reading: Chapter 11.1-11.3 ANNOUNCEMENTS Midterm #1 (Thursday 10/11, 3:30PM-5:00PM) location: 106 Stanley Hall: Students with last names starting with A-L 306 Soda Hall: Students with last names starting with M-Z EECS Dept. policy re: academic dishonesty will be strictly followed! HW#7 is posted online.

2
EE105 Fall 2007Lecture 13, Slide 2Prof. Liu, UC Berkeley Cascoding Cascode? Recall that the output impedance seen looking into the collector of a BJT can be boosted by as much as a factor of , by using a BJT for emitter degeneration. If an extra BJT is used in the cascode configuration, the maximum output impedance remains r o1.

3
EE105 Fall 2007Lecture 13, Slide 3Prof. Liu, UC Berkeley Cascode Amplifier Recall that voltage gain of a cascode amplifier is high, because R out is high. If the input is applied to the base of Q 2 rather than the base of Q 1, however, the voltage gain is not as high. – The resulting circuit is a CE amplifier with emitter degeneration, which has lower G m.

4
EE105 Fall 2007Lecture 13, Slide 4Prof. Liu, UC Berkeley Review: Sinusoidal Analysis Any voltage or current in a linear circuit with a sinusoidal source is a sinusoid of the same frequency ( ). – We only need to keep track of the amplitude and phase, when determining the response of a linear circuit to a sinusoidal source. Any time-varying signal can be expressed as a sum of sinusoids of various frequencies (and phases). Applying the principle of superposition: – The current or voltage response in a linear circuit due to a time-varying input signal can be calculated as the sum of the sinusoidal responses for each sinusoidal component of the input signal.

5
EE105 Fall 2007Lecture 13, Slide 5Prof. Liu, UC Berkeley High Frequency “Roll-Off” in A v Typically, an amplifier is designed to work over a limited range of frequencies. – At “high” frequencies, the gain of an amplifier decreases.

6
EE105 Fall 2007Lecture 13, Slide 6Prof. Liu, UC Berkeley A v Roll-Off due to C L A capacitive load (C L ) causes the gain to decrease at high frequencies. – The impedance of C L decreases at high frequencies, so that it shunts some of the output current to ground.

7
EE105 Fall 2007Lecture 13, Slide 7Prof. Liu, UC Berkeley Frequency Response of the CE Stage At low frequency, the capacitor is effectively an open circuit, and A v vs. is flat. At high frequencies, the impedance of the capacitor decreases and hence the gain decreases. The “breakpoint” frequency is 1/(R C C L ).

8
EE105 Fall 2007Lecture 13, Slide 8Prof. Liu, UC Berkeley Amplifier Figure of Merit (FOM) The gain-bandwidth product is commonly used to benchmark amplifiers. – We wish to maximize both the gain and the bandwidth. Power consumption is also an important attribute. – We wish to minimize the power consumption. Operation at low T, low V CC, and with small C L superior FOM

9
EE105 Fall 2007Lecture 13, Slide 9Prof. Liu, UC Berkeley Bode Plot The transfer function of a circuit can be written in the general form Rules for generating a Bode magnitude vs. frequency plot: – As passes each zero frequency, the slope of |H(j )| increases by 20dB/dec. – As passes each pole frequency, the slope of |H(j )| decreases by 20dB/dec. A 0 is the low-frequency gain zj are “zero” frequencies pj are “pole” frequencies

10
EE105 Fall 2007Lecture 13, Slide 10Prof. Liu, UC Berkeley Bode Plot Example This circuit has only one pole at ω p1 =1/(R C C L ); the slope of |A v |decreases from 0 to -20dB/dec at ω p1. In general, if node j in the signal path has a small- signal resistance of R j to ground and a capacitance C j to ground, then it contributes a pole at frequency (R j C j ) -1

11
EE105 Fall 2007Lecture 13, Slide 11Prof. Liu, UC Berkeley Pole Identification Example

12
EE105 Fall 2007Lecture 13, Slide 12Prof. Liu, UC Berkeley High-Frequency BJT Model The BJT inherently has junction capacitances which affect its performance at high frequencies. Collector junction: depletion capacitance, C Emitter junction: depletion capacitance, C je, and also diffusion capacitance, C b.

13
EE105 Fall 2007Lecture 13, Slide 13Prof. Liu, UC Berkeley BJT High-Frequency Model (cont’d) In an integrated circuit, the BJTs are fabricated in the surface region of a Si wafer substrate; another junction exists between the collector and substrate, resulting in substrate junction capacitance, C CS. BJT cross-sectionBJT small-signal model

14
EE105 Fall 2007Lecture 13, Slide 14Prof. Liu, UC Berkeley Example: BJT Capacitances The various junction capacitances within each BJT are explicitly shown in the circuit diagram on the right.

15
EE105 Fall 2007Lecture 13, Slide 15Prof. Liu, UC Berkeley Transit Frequency, f T The “transit” or “cut-off” frequency, f T, is a measure of the intrinsic speed of a transistor, and is defined as the frequency where the current gain falls to 1. Conceptual set-up to measure f T

16
EE105 Fall 2007Lecture 13, Slide 16Prof. Liu, UC Berkeley Dealing with a Floating Capacitance Recall that a pole is computed by finding the resistance and capacitance between a node and GROUND. It is not straightforward to compute the pole due to C 1 in the circuit below, because neither of its terminals is grounded.

17
EE105 Fall 2007Lecture 13, Slide 17Prof. Liu, UC Berkeley Miller’s Theorem If A v is the voltage gain from node 1 to 2, then a floating impedance Z F can be converted to two grounded impedances Z 1 and Z 2 :

18
EE105 Fall 2007Lecture 13, Slide 18Prof. Liu, UC Berkeley Miller Multiplication Applying Miller’s theorem, we can convert a floating capacitance between the input and output nodes of an amplifier into two grounded capacitances. The capacitance at the input node is larger than the original floating capacitance.

19
EE105 Fall 2007Lecture 13, Slide 19Prof. Liu, UC Berkeley Application of Miller’s Theorem

20
EE105 Fall 2007Lecture 13, Slide 20Prof. Liu, UC Berkeley Small-Signal Model for CE Stage

21
EE105 Fall 2007Lecture 13, Slide 21Prof. Liu, UC Berkeley … Applying Miller’s Theorem Note that p,out > p,in

22
EE105 Fall 2007Lecture 13, Slide 22Prof. Liu, UC Berkeley Direct Analysis of CE Stage Direct analysis yields slightly different pole locations and an extra zero:

23
EE105 Fall 2007Lecture 13, Slide 23Prof. Liu, UC Berkeley Input Impedance of CE Stage

Similar presentations

Presentation is loading. Please wait....

OK

EENG 3520: Electronics II Lecture 1 Oluwayomi Adamo.

EENG 3520: Electronics II Lecture 1 Oluwayomi Adamo.

© 2018 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on chromosomes and chromatin are both made Ppt on db2 mainframes vs servers Ppt on game theory john Ppt on effective leadership skills Ppt on bmc remedy service Ppt on human resources accounting Ppt on data collection methods and instruments Ppt on birds for kindergarten Ppt on mind reading phones Ppt on dairy farming project in india