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Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 1 Introduction to Electronic Circuit Design.

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Presentation on theme: "Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 1 Introduction to Electronic Circuit Design."— Presentation transcript:

1 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 1 Introduction to Electronic Circuit Design Richard R. Spencer Mohammed S. Ghausi

2 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 2 Figure 11-1 Ideal filter transfer function: (a) low-pass, (b) high-pass, (c) bandpass, (d) bandstop (or notch), and (e) allpass.

3 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 3 Figure 11-2 (a) The Bode magnitude plot and (b) phas plot for an ideal low-pass filter with cutoff frequency c = 1 rad/s and delay t p = 1 s. (c) The impulse response of the filter and (d) the step response.

4 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 4 Figure 11-3 The pole locations of a Butterworth transfer function with N = 4. The poles are equally spaced around the left half of a unit circuit and are symmetric about the real axis.

5 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 5 Figure 11-4 The Butterworth magnitude responses for N = 1, 2, 3, and 4.

6 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 6 Figure 11-5 Specifications for a low-pass filter. A transfer function that meets these specifications is also shown.

7 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 7 Figure 11-8 Magnitude and phase of the standard second-order transfer function for Q = 1, 0.707, and 0.3.

8 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 8 Figure 11-9 The Chebyshev magnitude responses for N = 3 and 4 with = (a 1-dB ripple). The frequency is normalized to the edge of the ripple band, instead of the cutoff frequency.

9 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 9 Figure (a) Ideal bandpass characteristics. (b) Practical bandpass characteristics.

10 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 10 Figure A11-1 (a) A message signal and (b) the resulting amplitude-modulated signal.

11 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 11 Figure (a) Low-pass pole location. (b) Corresponding bandpass pole locations found using the narrowband low-pass-to-bandpass transformation.

12 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 12 Figure The Butterworth bandpass magnitude response.

13 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 13 Figure A feedback amplifier with a frequency-dependent feedback network.

14 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 14 Figure An RC integrator.

15 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 15 Figure A switched-capacitor integrator.

16 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 16 Figure (a) The switched-capacitor integrator. (b) The nonoverlapping clocks.

17 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 17 Figure A transversal, or tapped-delay line, FIR filter.

18 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 18 Figure Two single-stage single-tuned amplifiers: (a) a stage with voltage and current gain (common merge) and (b) a stage with voltage gain (common control). Figure The small-signal AC equivalent circuit for the amplifier in Figure 11-35(a).

19 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 19 Figure Universal resonance curve for a single-tuned amplifier.

20 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 20 Figure (a) Pole-zero plot of a stagger-tuned maximally flat magnitude design using two single-tuned stages. (b) Magnitude responses for the individual tuned circuits and the overall stagger-tuned design.

21 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 21 Figure The block diagram of a basic PLL. Figure The VCO control voltage and loop input voltage for a PLL when tracking changes in the input frequency.

22 Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 11, slide 22 Figure A Laplace-domain block diagram for the PLL when locked.


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