Figure 12–1 Basic computer block diagram.

Name: Figure 12–1 Basic computer block diagram.
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Description: Figure 12–1 Basic computer block diagram.

Figure 12–1 Basic computer block diagram.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12– Basic block diagram of a typical computer system including common peripherals. The computer itself is shown within the gray block. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12–3 Thomas L. Floyd Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12–4 The 8086/8088 has two separate internal units, the EU and the BIU.

Figure 12–5 The internal organization of the 8088 microprocessor.

Figure 12– Nonoverlapping and overlapping segments in the first 1 MB of memory. Each segment represents 64 kB. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12– Formation of the 20-bit physical address from the segment base address and the offset address. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12–8 Illustration of the segmented addressing method.

Figure 12–11 The general register set.

Figure 12–12 The status and control flags.

Figure 12–13 Registers for the Intel processors from 8086/8088 through Pentium.

Figure 12–14 Hierarchy of programming languages relative to computer hardware.

Figure 12–15 Assembly to machine conversion using an assembler.

Figure 12–16 High-level to machine conversion with a compiler.

Figure 12–17 Machine independence of a program written in a high-level language.

Figure 12–18 Flowchart for adding a list of numbers.

Figure 12–19 Steps in beginning to execute the addition program with Debug.

Figure 12–20 Last portion of tracing the addition program
Figure 12– Last portion of tracing the addition program. The sum 00F1 is shown in blue with the low part (F1) given first. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12–21 Flowchart. The variable BIG represents the largest value.

Figure 12–22 Listing of Debug portion of program.

Figure 12–23 Data before and after a run.

Figure 12–24 The basic polled I/O configuration.

Figure 12–25 A basic interrupt-driven I/O configuration.

Figure 12–26 A memory I/O transfer handled by the CPU.

Figure 12–27 A DMA transfer. Thomas L. Floyd Digital Fundamentals, 9e

Figure 12– The interconnection of microprocessor-based system components by a bidirectional, multiplexed bus. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 12–29 An example of a handshaking sequence.

Figure 12–30 Tristate buffer interface to a bus.

Figure 12–31 Method of indicating tristate outputs on an IC device.

Figure 12–32 Tristate buffer symbols.

Figure 12–33 Tristate buffer operation.

Figure 12–34 Multiplexed I/O operation.

Figure 12–35 Simplified illustration of the basic bus system in a typical personal computer.

Figure 12–36 The RS-232C 25-pin connector plug.

Figure 12–37 The RS-232C pin assignments and signals for both connector versions.

Figure 12–38 Example of a computer system with USB interfacing.

Figure 12–39 A typical IEEE 488 (GPIB) connection.

Figure 12–40 Timing diagram for the GPIB handshaking sequence.

Figure 12–41 A bus extender and modem can be used for interfacing remote GPIB systems.

Figure 12–42 SCSI 25-pin connector.

Figure 12–1 Basic computer block diagram.

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Figure 12–1 Basic computer block diagram.

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