1. Radiation Characterization of a Hardened 0.22  m Anti-Fuse Field Programmable Gate Array R.J. Nejad 1, P.A. Rickey 2, K. Konadu 2, W.J. Stapor 2, P.T. McDonald 2, W. Heidergott 3 1 Welkin Associates LTD., Chantilly VA 20151 2 Stapor Research Inc., Chantilly VA 20151 3 General Dynamics C4 Systems, Scottsdale AZ 85251 May 10, 2006

2. November 2005 2 Outline Introduction Target device personalities Measurements methodology Heavy ions Protons Data reduction and analysis Summary

3. November 2005 3 Goal VERIFY SUITABILITY OF UMC ACTEL RTSX-SU SERIES FPGA DEVICES FOR USE IN LEO

4. November 2005 4 Background Change to UMC foundry devices required accurate SEE rate assessment SEE rates for MEC foundry devices were known –No empirical reason to expect that UMC devices have the same rates Biggest problem for any new device is Destructive SEE (DSEE) –Not empirically verified with applicable particle radiation and suitable operating conditions Limited existing NASA/Actel data was encouraging

5. November 2005 5 Limited Actel UMC SEU Data

6. November 2005 6 Issue With Existing Data

7. November 2005 7 Vendor Data

8. November 2005 8 Subsequent Vendor Data

9. November 2005 9 Path Developed suitable RTSX 32 & 72 target device personalities Operated at 33, 50, and 100 MHz and as-used biasing TAMU Heavy ion irradiations –Verify No Destructive SEE Up to LET 40 MeV/(mg/cm 2 ) Minimum 1E7 particles/cm 2 –Measured & analyzed Non-Destructive SEE cross sections & rates IUCF Proton irradiations –Verify No Destructive SEE Up to 197 MeV –Measured & analyzed Non-Destructive SEE cross sections & rates –Accounted for accumulated proton dose (TID) during irradiations

10. November 2005 10 Target Device Personalities Built from Actel standard library Designed to reflect as-used configuration by providing combinatorial logic between flip flops –Follows application logic architecture –Allows separable cross sections from particle radiation Organized as separate ‘threads’ –Basic logic block typically consists of 10 buffers, flip flops, or logic functions –Thread made of multiple concatenated blocks –Thread size is easily configurable –Our threads were tailored to cover application functionality

11. November 2005 11 Basic Test Circuits 72S test circuits are a superset of the 32S circuits Common 72S & 32S threads –400 R-cell flip flops (DF1CB) –400 C-cell flip flops (DF1CB_CC) –400 R-cell flip flops (DF1CB) & 400 C-cell 2 level combinatorial logic (CM8) –I/O Buffer thread 20 R-cell flip flops 80 Input 80 Output cells external loop

12. November 2005 12 Common Target Blocks DF1CB (A) DF1CB_CC (B) I/O (C) DF1CB & CM8 (F) Combinatorial logic

13. November 2005 13 Target Distribution SX72 and SX32 targets loaded up and running at speed

14. November 2005 14 Design Advantages Used long shift registers to increase sample size –Compared to previous measurements Error counting is automated (10 channels simultaneously) Separable SEE cross section data SEE susceptibility measured at speed –R-cell –C-cell flip flop Combinatorial SEE rate characterized vs frequency I/O-cell SEE characterized Clock SEE

15. November 2005 15 SX72 Measurement Circuit Summary REF LETTER CIRCUITFUNCTION TEST EQUIPMENT A R Cell Flip Flop Test Circuit DF1CB Chain of 400 R Cell flip flops used to measure R Cell cross section BERT B C Cell Flip Flop Test Circuit DF1CB_CC Chain of 400 C Cell flip flopsBERT C I/O Buffer Test Circuit Chain of 80 R Cell flip flops interleaved with 80 Input & 80 Output blocks with external pin looping BERT D C Cell Test Circuit DF1CB, XOR3 & BUF Chain of R Cell flip flops interleaved with C Cell combinatorial logic BERT E C Cell Test DFC1B, XOR3B Chain of R Cell flip flops interleaved with C Cell 1 level combinatorial logic BERT F C Cell Test DF1CB, CM8 Chain of 400 R Cell flip flops interleaved with 400 C Cell 2 level combinatorial logic BERT G R Cell TMR DF1CB Chain of TMR R Cell Flip Flops with 3 R Cells and 1 C Cell majority voter BERT H R Cell Enable DFE3C Chain of R-cell flip flops with enableBERT J, K Counter Two counters and comparatorsEvent Counter L Clock Test Circuit HCLK Monitors clock networks for runt pulsesOscilloscope M Clock Test Circuit CLKA Monitors clock networks for runt pulsesOscilloscope N Clock Test Circuit QCLK Monitors clock networks for runt pulsesOscilloscope P Buffer Test Circuit Chain of buffers used to measure changes in propagation delay with TID Signal Generator Oscilloscope, (offline)

16. November 2005 16 Supply Voltage & IO Configuration Test design is configured for 2.5V core voltage and 3.3V IO voltage All Inputs are configured as –LVTTL logic threshold –Power Up State ‘none’ (i.e. Neither a pull-up nor a pull- down resistor) All Outputs are configured as –LVTTL standard –High slew –Power Up State ‘none’ (i.e. Neither a pull-up nor a pull- down resistor) –35 pF of capacitive loading

17. November 2005 17 SX72 Target Dimensions 1.5 cm × 0.8 cm die

18. November 2005 18 Measurement Methodology Measured bit errors in each thread using a PRBS input sequence –Developed a Xilinx FPGA based BERT to simultaneously exercise all test threads –Scaled to 10 receiver channels –F MAX > 100 MHz –RS-232 Command & Control –Uses 2 7 -1 or 2 10 -1 PRBS sequence (2 10 -1 used) Measured supply current and propagation delay for TID degradation –Power supply meter for current –Signal generator and oscilloscope for prop delay

19. November 2005 19 Measurement Setup DUT TARGET CAVE RECEIVERSDRIVERS USER CAVE PWB Xilinx BERT & EVENT COUNT 2X 10X O’SCOPE LAPTOP LAN RS232 SIG GEN DATA RATE SIG GEN COMM RATE PC 44 10

20. November 2005 20 TAMU Beams IonZA Energy (MeV/amu) Kinetic Energy (MeV)  dE/dx in (Si) (MeV/(mg/cm 2 )) Range (Si) (μm) 129 Xe5412922.6629230.21739.6255 84 Kr368415.4512980.18025177 84 Kr368423.1219420.21920.1302 40 Ar18403.851540.0911540 40 Ar18409.603840.14210123 40 Ar184023.809520.2225.6463

21. November 2005 21 Measurement Equipment DUT BERT INTERFACE

22. November 2005 22 TAMU Target Beam Alignment

23. November 2005 23 TAMU User Cave

24. November 2005 24 IUCF Measurements Setup Beam AlignmentEquipment Cart

25. November 2005 25 Analysis For each test thread (heavy ions & protons) –Channel Cross section per bit (# of errors) / (particle fluence) –Extracted Cross sections R Cell, CC Cell, C Cell Combinatorial, IOBUF Function of LET, Cell Type, and Clock Rate Propagation delay (thread P) –Fluence –Total Ionizing Dose (protons) DUT supply current –Fluence –Total Ionizing Dose (protons)

26. November 2005 26 Cross Section Extraction RAW Channel Measurement Data Matrix Extraction Channel  RUN # Events RUN Fluence RUN Run  R Cell C Cell IO Cell CC Cell Statistical Combination Mean  CELL and Uncertainty

27. November 2005 27 Thread Cell Distribution Circuit Threads BERT Channel R Cell Count C Cell Count I/O Buffer Count CC Flip Flop Count IOBUF7801*163*0 DFC1B3400020 DFC1B_CM86400 20 DFC1B_CC4002400** * IOBUF chain contains a MUX (C Cell) and 3 I/O Buffers in the circuit to enable/disable the chain ** DFC1B contains 800 C Cells configured as 400 CC Flip Flops Four circuit threads common to both 32SX and 72SX targets were used to extract R Cell, C Cell, IO Cell and CC Cell

28. November 2005 28 Matrix Math 4 unknowns –R Cell cross section, R –I/O Buffer cross section, I/O –C Cell cross section, C –CC Flip Flop cross section, CC 4 test threads –DFC1B (thread A) –DFC1B_CC (thread B) –DFC1B_CM8 (thread F) –IOBUF (thread C) Together they form 4 unknowns and 4 equations –Equations that describe the threads can be written in matrix form Matrix algebra solution

29. November 2005 29 Matrix Form

30. November 2005 30 Cell Data Cross Sections Heavy ion cross sections measured for a range of LET values from ~5 to 40 MeV/(mg/cm 2 ) No clear LET thresholds observed –No need to include LET threshold –No need for traditional and somewhat limited Weibul Cell cross section data analyzed using a power law function (  = A  LET B ) –Conservative approach –Function has the key features of the data and fits well for IO, C, CC, and R Cell datasets –Accounts for potentially small but non-zero contributions from very low LET values Includes 0,0 data point

31. November 2005 31 Comments on Multiple Bit Errors Multiple bit errors (MBE) are defined as consecutive bits in error from a single particle strike Very few MBE were observed on all channels for clock rates < 100 MHz Most MBE observed at 100 MHz –Especially in the IOBUF channel –Interaction between SET width and clock width –System and design specific issue –All bits in error were treated as single-bit SEU for conservative rate estimates in this analysis

32. November 2005 32 Sample MBE Distribution @ 33 MHz Run 14, Type 72, LET 24.8 MeV/(mg/cm 2 ) Summary Statistics ================== (bits) (err/s) (s/chan) (bits) (bits) (bits) (bits) CH ERRORS SYNCH RESET ROLLOVER RATE(/s) ELAPSED 1-BIT 2-BIT 3-BIT 4>-BIT -- ------ ----- ----- -------- -------- ------- ------ ------ ------ ------ 1 2 1 0 0 0.25E-02 813 2 0 0 0 2 4 1 0 0 0.49E-02 813 4 0 0 0 3 4 1 0 0 0.49E-02 813 4 0 0 0 4 27 1 0 0 0.33E-01 813 27 0 0 0 5 0 1 0 0 0.00E+00 813 0 0 0 0 6 4 1 0 0 0.49E-02 813 4 0 0 0 7 0 1 0 0 0.00E+00 813 0 0 0 0 8 0 1 0 0 0.00E+00 813 0 0 0 0 9 1 1 0 0 0.12E-02 813 1 0 0 0 10 1 1 0 0 0.12E-02 813 1 0 0 0

33. November 2005 33 Sample MBE Distribution @ 100 MHz Run 12, Type 72, LET 24.8 MeV/(mg/cm 2 ) Summary Statistics ================== (bits) (err/s) (s/chan) (bits) (bits) (bits) (bits) CH ERRORS SYNCH RESET ROLLOVER RATE ELAPSED 1-BIT 2-BIT 3-BIT 4>-BIT -- ------ ----- ----- -------- -------- ------- ------ ------ ------ ------ 1 24 1 0 0 0.28E-01 868 20 2 0 0 2 29 1 0 0 0.33E-01 868 29 0 0 0 3 46 1 0 0 0.53E-01 868 44 1 0 0 4 123 1 0 0 0.14E+00 868 113 5 0 0 5 4 1 0 0 0.46E-02 868 0 2 0 0 6 51 1 0 0 0.59E-01 868 51 0 0 0 7 333 1 0 0 0.38E+00 868 32 59 32 16 8 19 1 0 0 0.22E-01 868 19 0 0 0 9 11 1 0 0 0.13E-01 868 5 3 0 0 10 12 1 0 0 0.14E-01 868 6 3 0 0

34. November 2005 34 All R Cell Data

35. November 2005 35 R CELL 10, 50, & 100 MHz

36. November 2005 36 C CELL 10, 50, & 100 MHz

37. November 2005 37 IO Buffer 10, 50, & 100 MHz

38. November 2005 38 CC Cell

39. November 2005 39 Cell Sensitivity & Clock Speed All cells show CLOCK SPEED (CLK) dependence Can be parameterized

40. November 2005 40 Proton Measurements Heavy ion measurements suggested proton SEE sensitivity IUCF measurements at 197 MeV Each sample (S/N 1-6, 8) received a fluence of 1.7E12 particles/cm 2 at an average flux of 8.22E8 particles/(cm 2  s) –Equivalent to ~100 krad(Si) Only IOBUF upsets were observed for protons –Cross section comparable to PROFIT Model predictions Propagation delay measured as a function of total ionizing dose

41. November 2005 41 IOBUF Proton Cross Section

42. November 2005 42 Proton Propagation Delay (P d ) Measurement Measured over a chain of inverters up to 100 krad(Si) ΔP d(min) @ 1% ΔP d(max) @ 5% ΔP d(avg) @ 3% DeviceDevice #ΔP d (%) RTSX3214% RTSX3223% RTSX3234% RTSX3242% RTSX7251% RTSX7264% RTSX7285%

43. November 2005 43 Summary Characterized UMC Actel RT54SX 32 & 72 FPGA devices –Heavy ions & Protons –Operational speeds up to 100 MHz –Extends previous investigations Innovative test thread approach –Enables separable cell type cross sections –As-used architecture –Scalable to complex applications No destructive SEE observed SEE cross sections determined for R, C, IO, & CC cells –IO Buffers are the most sensitive –Clock dependency –All cells (TMR included) have non-zero response to heavy ions Proton total dose up to ~100 krad(Si) Space particle radiation effects can be mitigated through design