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Processes and Operating Systems

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Presentation on theme: "Processes and Operating Systems"— Presentation transcript:

1 Processes and Operating Systems
Chapter 6 Processes and Operating Systems Copyright © 2013 Elsevier Inc. All rights reserved.

2 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.1 Scheduling overhead is paid for at a nonlinear rate. Copyright © 2013 Elsevier Inc. All rights reserved.

3 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.2 Example definitions of initiation times and deadlines. Copyright © 2013 Elsevier Inc. All rights reserved.

4 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.3 A sequence of processes with a high initiation rate. Copyright © 2013 Elsevier Inc. All rights reserved.

5 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.4 Data dependencies among processes. Copyright © 2013 Elsevier Inc. All rights reserved.

6 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.5 Communication among processes at different rates. Copyright © 2013 Elsevier Inc. All rights reserved.

7 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.6 Scheduling states of a process. Copyright © 2013 Elsevier Inc. All rights reserved.

8 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.7 Sequence diagram for preemptive execution. Copyright © 2013 Elsevier Inc. All rights reserved.

9 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.8 Sequence diagram for a FreeRTOS.org context switch. Copyright © 2013 Elsevier Inc. All rights reserved.

10 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.9 An active class in UML. Copyright © 2013 Elsevier Inc. All rights reserved.

11 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.10 A collaboration diagram with active and normal objects. Copyright © 2013 Elsevier Inc. All rights reserved.

12 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.11 An example of rate-monotonic scheduling. Copyright © 2013 Elsevier Inc. All rights reserved.

13 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.12 C code for rate-monotonic scheduling. Copyright © 2013 Elsevier Inc. All rights reserved.

14 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.13 C code for earliest-deadline-first scheduling. Copyright © 2013 Elsevier Inc. All rights reserved.

15 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.14 Shared memory communication implemented on a bus. Copyright © 2013 Elsevier Inc. All rights reserved.

16 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.15 Message passing communication. Copyright © 2013 Elsevier Inc. All rights reserved.

17 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.16 Use of a UML signal. Copyright © 2013 Elsevier Inc. All rights reserved.

18 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.17 Sequence diagram for RTOS interrupt latency. Copyright © 2013 Elsevier Inc. All rights reserved.

19 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.18 Interrupt latency during a critical section. Copyright © 2013 Elsevier Inc. All rights reserved.

20 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.19 An L-shaped usage distribution. Copyright © 2013 Elsevier Inc. All rights reserved.

21 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.20 Architecture of a power-managed system. Copyright © 2013 Elsevier Inc. All rights reserved.

22 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.21 The Advanced Configuration and Power Interface and its relationship to a complete system. Copyright © 2013 Elsevier Inc. All rights reserved.

23 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.22 Windows CE layer diagram. Copyright © 2013 Elsevier Inc. All rights reserved.

24 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.23 OAL architecture in Windows CE. Copyright © 2013 Elsevier Inc. All rights reserved.

25 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.24 Kernel and user address spaces in Windows CE. Copyright © 2013 Elsevier Inc. All rights reserved.

26 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.25 User address space in Windows CE. Copyright © 2013 Elsevier Inc. All rights reserved.

27 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.26 Sequence diagram for an interrupt. Copyright © 2013 Elsevier Inc. All rights reserved.

28 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.27 The ADPCM coding scheme. Copyright © 2013 Elsevier Inc. All rights reserved.

29 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.28 An ADPCM compression system. Copyright © 2013 Elsevier Inc. All rights reserved.

30 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.29 Class diagram for the answering machine. Copyright © 2013 Elsevier Inc. All rights reserved.

31 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.30 Physical class interfaces for the answering machine. Copyright © 2013 Elsevier Inc. All rights reserved.

32 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.31 The message classes for the answering machine. Copyright © 2013 Elsevier Inc. All rights reserved.

33 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.32 Operational classes for the answering machine. Copyright © 2013 Elsevier Inc. All rights reserved.

34 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.33 State diagram for the Controls activate behavior. Copyright © 2013 Elsevier Inc. All rights reserved.

35 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.34 State diagrams for the record-msg and playback-msg behaviors. Copyright © 2013 Elsevier Inc. All rights reserved.

36 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.35 Hardware platform for the answering machine. Copyright © 2013 Elsevier Inc. All rights reserved.

37 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.36 Engine block diagram. Copyright © 2013 Elsevier Inc. All rights reserved.

38 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.37 Requirements for the engine controller. Copyright © 2013 Elsevier Inc. All rights reserved.

39 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.38 Periods for data in the engine controller. Copyright © 2013 Elsevier Inc. All rights reserved.

40 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.39 Class diagram for the engine controller. Copyright © 2013 Elsevier Inc. All rights reserved.

41 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.40 State diagram for throttle position sensing. Copyright © 2013 Elsevier Inc. All rights reserved.

42 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.41 State diagram for injector pulse width. Copyright © 2013 Elsevier Inc. All rights reserved.

43 Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 6.42 State diagram for spark advance angle. Copyright © 2013 Elsevier Inc. All rights reserved.

44 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.1 Copyright © 2013 Elsevier Inc. All rights reserved.

45 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.2 Copyright © 2013 Elsevier Inc. All rights reserved.

46 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.3 Copyright © 2013 Elsevier Inc. All rights reserved.

47 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.4 Copyright © 2013 Elsevier Inc. All rights reserved.

48 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.5 Copyright © 2013 Elsevier Inc. All rights reserved.

49 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.6 Copyright © 2013 Elsevier Inc. All rights reserved.

50 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.7 Copyright © 2013 Elsevier Inc. All rights reserved.

51 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.8 Copyright © 2013 Elsevier Inc. All rights reserved.

52 Copyright © 2013 Elsevier Inc. All rights reserved.
UN Figure 6.9 Copyright © 2013 Elsevier Inc. All rights reserved.


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