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April 28th, 2011Timing Workshop, Chicago Paul Scherrer Institute The role of analog bandwidth and signal-to-noise in timing for waveform digitizing Stefan Ritt

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April 28th, 2011Timing Workshop, Chicago Timing measurement How can we measure timing in an optimal system?

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Stefan RittApril 28th, 2011Timing Workshop, Chicago The ideal digitized signal No noise Always same height Derive time from threshold crossing with interpolation No noise Always same height Derive time from threshold crossing with interpolation Threshold Timing determined by “aperture jitter”

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Stefan RittApril 28th, 2011Timing Workshop, Chicago Aperture jitter Datasheet AD9222 (Analog Devices) PLL Switched Capacitor Array Flash ADC Determined by write switch jitter plus inverter jitter Measurements indicate typical value 2-5 ps for current designs Determined by write switch jitter plus inverter jitter Measurements indicate typical value 2-5 ps for current designs Data sheet: <1ps Measured indirectly though side-band of sine signal AD Application Note AN501: 50fs (clk) + 190fs (ADC) Data sheet: <1ps Measured indirectly though side-band of sine signal AD Application Note AN501: 50fs (clk) + 190fs (ADC)

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Stefan RittApril 28th, 2011Timing Workshop, Chicago Aperture jitter of clock distribution

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Stefan RittApril 28th, 2011Timing Workshop, Chicago The varying digitized signal Signals with different amplitude trigger at different times (“time walk”) Upper threshold Time walk correction Multi-level threshold Constant-fraction discrimination Time walk correction Multi-level threshold Constant-fraction discrimination Lower threshold J.-F. Genat et al., arXiv:0810.5590 (2008)

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Stefan RittApril 28th, 2011Timing Workshop, Chicago Effects of analog BW How does the analog bandwidth affect the timing ?

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Stefan RittApril 28th, 2011Timing Workshop, Chicago Realistic signal with noise voltage noise band of signal timing jitter arising from voltage noise timing jitter is much smaller for faster rise-time Effect of rise time Noise Timing Noise affects timing!

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Nyquist-Shannon Theorem If a function x(t) contains no frequencies higher than F Hertz, it is completely determined by giving its ordinates at a series of points spaced 1/2F seconds apart. If a detector produces frequencies up to 500 MHz (0.6 ns rise time), all information from that detector is recorded if sampled at 1 GSPS with good enough signal-to-noise (SNR) ratio Sampling speed above Nyquist adds redundant points which improve the SNR Nyquist-Shannon fulfilled Nyquist-Shannon not fulfilled

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Does higher sampling speed help? 20.08.2014PSI, Higher sampling speed adds only redundant points if Nyquist is fulfilled If noise comes from chip → reduce noise √2 Equivalent to double sampling of points Higher sampling speed adds only redundant points if Nyquist is fulfilled If noise comes from chip → reduce noise √2 Equivalent to double sampling of points =

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Stefan RittApril 28th, 2011Timing Workshop, Chicago How is timing resolution affected? voltage noise u timing uncertainty t signal height U rise time t r number of samples on slope Simplified estimation!

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Stefan RittApril 28th, 2011Timing Workshop, Chicago How is timing resolution affected? U uu fsfs f 3db tt 100 mV1 mV2 GSPS300 MHz ∼ 10 ps 1 V1 mV2 GSPS300 MHz1 ps 100 mV1 mV20 GSPS3 GHz0.7 ps 1V1 mV10 GSPS3 GHz0.1 ps today: optimized SNR: next generation: includes detector noise in the frequency region of the rise time and aperture jitter next generation optimized SNR: How to achieve this? Assumes zero aperture jitter

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Stefan Ritt S/N ratio goes linearly into timing resolution! Analog BW and sampling speed will soon hit some “hard” limits (3-5 GHz, ~20 GSPS) Preamplifier makes sense if detector noise is smaller than SCA internal noise In the end, higher timing resolution will be the battle of noise → Eric’s talk tomorrow Effect of S/N April 28th, 2011Timing Workshop, Chicago PCB Det. f SCA ADC

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Stefan RittApril 28th, 2011Timing Workshop, Chicago What limits the BW? Which are the crucial points in the signal chain?

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Stefan Ritt PCB April 28th, 2011Timing Workshop, Chicago Detector (covered in next talks) Connector (LEMO connector has a BW of ∼ 500 MHz) Cable (RG58: 5 m has a -3db BW of 1 GHz) PCB Preamplifier Chip package On-chip bus Analog cell switch Storage capacitor Signal Chain Det. Chip C par

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Stefan RittApril 28th, 2011Timing Workshop, Chicago Amplifier C par 750 MHz ∼ 40pF

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Stefan RittApril 28th, 2011Timing Workshop, Chicago Effects from the chip → Tomorrow’s talk

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Stefan Ritt Conclusions April 28th, 2011Timing Workshop, Chicago Optimize BW of detector Optimize BW of transmission Optimize S/N for digitization Fit digitization B/W to signal Fulfill Nyquist- Shannon

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