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Basic Knowledge of Data Converters

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Agenda Data Converter Overview ADC/DAC Basics –Sampling Theory –ADC Architectures SAR Delta-Sigma Pipeline Flash –DAC Architectures R-2R String Data Converter Specifications / Test (how to get them from DATASHEET) –DC Spec. –AC Spec. –ADC/DAC Nomenclature

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What is ADC Analog to Digital

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What is DAC Digital to Analog

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ADC/DAC Basic –Sampling Theory –ADC Architectures Delta-Sigma SAR Pipeline Flash –DAC Architectures R-2R String

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Basic ADC Theory Analog signal is sampled The sampled analog signal is compared to one or more reference voltages The result of the comparison is converted by digital logic to a binary number.

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SHANNONS information theorem NYQUISTS Criteria n Shannon: u An analog signal with a Bandwidth of f a must be sampled at a rate f s >2f a in order to avoid the loss of information. u The Signal Bandwidth may extend from DC to f a (Baseband Sampling) or from f 1 to f 2, where f a = f 2 -f 1 (Undersampling, or Super-Nyquist). n Nyquist: u If f s <2f a, then a phenomenon called aliasing will occur. u Aliasing is used to advantage in undersampling applications

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Input Spectrum F(f) f1 f Sampled Spectrum G(f) f1 f fsfs+f12fs-f1 Sampled Output t g(t) t1t2t3t4 f(t4) f(t3) f(t2) f(t1) X= = * Sampling Function Unit Pulses h(t) t T Fourier Transform NYQUIST'S THEOREM: fs-f1 > f1 fs > 2 f1 Input Waveform f(t) t t1t2t3t4 * Sampling Spectrum H(f) f fs = 1/T2fs Nyquist region 14-8 Sampling Theory

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Oversampling

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Why Oversample? TO MOVE ALIASING FREQUENCY FURTHER FROM THE DESIRED SIGNAL. TO RELIEVE ANTIALIASING AND RECONSTRUCTION FILTER REQUIREMENTS –COST –COMPLEXITY –RESPONSE TO ALLOW FOR LOWER APPARANT INPUT NOISE BY FILTERING IN THE DIGITAL DOMAIN. TO ALLOW FOR LOWER APPARANT INPUT NOISE BY SPREADING THE QUANTIZING NOISE OVER A WIDER BANDWIDTH.

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Sampling ADC Quantization Noise OUTPUT SIGNAL RMS QUANTIZATION NOISE = q/ 12 f s 2 f s

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Effects of oversampling on Quantization Noise

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Analog signal f a f s has images (aliases) at |±Kf s ±f a |, K = 1, 2, 3,...

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Effect of oversampling on filter requirement

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Analog filter requirement for fo = 10MHz: f S = 30MSPS AND f S = 60MSPS

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Undersamplinig

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Why Undersample? The AC bandwidth of the analog portion of an ADC is usually wider than the maximum sample rate. Nyquist says that the BANDWIDTH not the FREQUENCY of the signal must be ½ sampling rate. You can process the spectrum at harmonics of the sample rate as well

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Undersampling

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Minimum sampling rate as a function of the ratio of the highest frequency to the total signal bandwidth f s B B = SIGNAL BANDWIDTH f = MAXIMUM SIGNAL FREQUENCY f = MINIMUM REQUIRED SAMPLING RATE MAX s B f

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Intermediate Frequency (IF) signal at 72.5MHz (±2MHz) is aliased between DC and 5MHz dcf s f s = MHz7f7f s = MHz 7f7f s 6f6f s 5f5f s 4f4f s 3f3f s 2f2f s s f = MSPS BASEBAND ALIAS: dc TO 5 MHz SIGNAL: 72.5 ± 2 MHz

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Anti-aliasing filter for undersampling f c f 1 TO f s - f 1

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Quantization Error Analog signals are continuous Digital signals have discrete values A digital word that is converted to an analog signal will always contain errors Quantization Error or Noise is dependent on the number of bits used in the conversion

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Quantization

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Data Converters Architectures ADCs –Delta Sigma –SAR –Pipeline –Flash DAC –R-2R –String Customers Talk Architecture??? Should you be scared - NO Can you handle it - TRY Just know the key characteristics and you have just focused in on your device selection

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- SAR - Pipeline - Flash - Delta Sigma A/D Converter

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ADC Architectures: Speed, Resolution, and Latency Analogy Delta Sigma –16 to 24 bits of resolution –Typically Slow 10SPS to 105kSPS –Long Latency –If I was a camera I would have my aperture open longer SAR –8 to 18 bits of resolution –~50kSPS to 4MSPS –No latency –If I was a camera I would be have fast shutter speed Pipeline –8 to 14 bits of resolution –Up to over 300 MSPS –Some clock cycle latency –I want to be a video camera when I grow up Flash –8 to 10 bits of resolution –Up to over 1 GSPS –no latency –I just want to be FLASH

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TI Analog to Digital Families Pipeline Accuracy (Resolution in bit) 300 M 100 M 10 M 1 M 500 k 100 k 10 k 1 k Delta Sigma Speed: Sample Rate in SPS SAR Advantages No Latency (happens immediately)No Latency High Resolution and Accuracy (<=18-bits) Typically Low Power Easy to Use and MultiplexDisadvantages Typically sample Rates Limited to Approximately 4 MHz Advantages Higher Speeds Higher Bandwidth Disadvantages Lower Resolution Pipeline Delay/Data Latency More power Delta Sigma Advantages High Resolution Low cost Low Power typically High Stability (averages and filters out noise)Disadvantages High Latency Low Speed typically

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ADC – Successive Approximation Register (SAR) Architecture An n bit SAR converter takes n cycles to complete a conversion. From most to least significant bit (MSB to LSB) simple compare functions are done and, when a bit is a 1, that amount of voltage is subtracted from the input signal. SARs are workhorse converters… easy to use… simple to understand… but are limited in both resolution and speed. TI has MANY SAR ADCs. Ref V IN MSB LSB Data Out fSfS +-+- S/H Clock SAR and Control Logic D/A Converter MSBLSB FS FS: Full Scale 0 FS 2

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Successive Approximation ADC

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ADC – Pipeline Architecture Pipeline converters are another high speed architecture. Several lower resolution converters are put together to result in a fast conversion time. Generally lower power and lower cost than Flash converters, the main disadvantage of a Pipeline converter is that it takes as many clock cycles as there are stages to output the data resulting in latency. PARALLEL DIGITAL OUTPUT ANALOG INPUT + - STAGE N + - STAGE 1 Sample Hold Amplifier SAMPLE HOLD AMPLIFIER Sample Hold Amplifier DAC REGISTER DAC ADC REGISTER ADC TI has many Pipeline converters!

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Latency SARs have none ….OK, just a little Aperture delay = 2ηs Conversion Time = 150ηs Acquisition Time ADS bits 4MSPS If it was a 12 bit pipeline with 2 bits/stage, you would need: Snapshot 150 ηs Conv t Delay = 6.6MSPS X 6 clock cycle delay = 40MSPS

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n-7n-6n-5 n-4n-3n-2n-1n Pipeline A/D Converter Timing and Data Latency Analog Input Clock Internal S/H Output Data Sample Points S1 S2 S3 S4 S5 S6 S7 S8 S9 Track Hold Track Hold Data Latency, 6.5 clock cycles n+3nn+7n+6n+5n+4n+2n+1

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Pipeline A/D Converter Signal Encoding: SAR vs. Pipeline SAR: Serial Encoding Sample #1 Pipeline: Parallel Encoding Sample #3 Sample #2 Sample #1 MSB LSB B2 B3 B4 B5 B6 B7 Conversion Time MSBLSBB2B3B4B5B6B7

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And Now for something completely different Delta Sigmas

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Delta-Sigma Overview What is a delta-sigma ADC? –A 1-bit converter that uses oversampling (can be multi-bit) –Delta = comparison with 1-bit DAC –Sigma = integration of the Delta measurement What is the advantage of delta-sigma? –Essentially digital parts which result in low cost –High resolution What are the disadvantages? –Limited frequency response –Most effective with continuous inputs –Latency 3

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Converters – Functional Block Diagram Analog Input 1-bit wide n-bits wide Digital Output Digital Filter Analog Modulator PGA Advantages: Minimum analog components Integrates easily with digital logic Oversampling reduces inband noise Disadvantages: Speed limited to upper audio range

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Delta-Sigma A/D Converters

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Delta-Sigma A/D Signal Path You are here

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Delta-Sigma A/D Signal Path TIME DOMAIN FREQUENCY DOMAIN

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Delta-Sigma A/D Signal Path

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TIME DOMAIN FREQUENCY DOMAIN

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Delta-Sigma A/D Signal Path TIME DOMAIN FREQUENCY DOMAIN

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Delta-Sigma A/D Signal Path

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TIME DOMAIN FREQUENCY DOMAIN

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Delta-Sigma A/D Signal Path

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TIME DOMAIN FREQUENCY DOMAIN

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Delta-Sigma A/D Signal Path SIGNAL FROM MODULATOR OUTPUT OF DECIMATING FILTER DECIMATING FILTER

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Oversampling, digital filter, NOISE SHAPING, AND DECIMATION Kf s fs2fs2 fsfs 2 Kf s 2 fs2fs2 fs2fs2 DIGITAL FILTER REMOVED NOISE QUANTIZATION NOISE = q / 12 q = 1 LSB ADC DIGITAL FILTER MOD DIGITAL FILTER fsfs Kf s DEC fsfs Nyquist Operation Oversampling + Digital Filter + Decimation Oversampling + Noise Shaping + Digital Filter + Decimation A B C DEC fsfs

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The Delta-Sigma Modulator To Digital Filter Signal input, X 1 X2X2 X3X3 X4X4 X5X5 Difference Amp Integrator Comparator (1-bit ADC) 1-bit DAC VMax Delta Sigma 4

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Delta-Sigma Modulator

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Averaging Filters 0V Full-scale Delta-Sigma Modulator DC input levels 1-bit data 1-bit data streams 1/2 full-scale input1/4 full-scale input3/4 full-scale input 111 0Average0Average1Average 1= 0.50= 0.251=

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The Frequency Domain Frequency F S / 2 FSFS Signal amplitude Quantization Noise SNR = 6.02N dB ; (for an N-bit ADC Sine wave input) Average noise floor (flat) Power

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Oversampling by K Times Frequency k F S / 2 k F S Average noise floor Oversampling by K times Power Same total noise, but spread over more frequencies SNR = 6.02N dB ; (for an N-bit ADC Sine wave input)

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The Digital Filter Frequency k F S / 2 k F S Noise removed by filter Oversampling by K times Ideal digital filter response BW Power SNR = 6.02N dB + 10 log(Fs/2*BW)

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Noise-Shaped Spectrum Frequency k F S / 2k F S Signal Amplitude The integrator serves as a highpass filter to the noise. The result is noise shaping Power SNR = 6.02N dB

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Vin(t)Integrator D/A CLK Dout(t) 1 st order Modulator

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Filtering the Shaped Noise Signal amplitude HF noise removed by the digital filter Digital filter response Frequency k F S / 2k F S Power

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The 2nd Order Delta-Sigma Modulator bit DAC 1-BIT ADCINTEGRATOR 1-BIT OUTPUT - + INTEGRATOR SPECTRAL QUANTIZATION NOISE DENSITY MODULATOR OUTPUT

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The Delta-Sigma Modulator

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Sampling speed vs. ENOB Fd

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ADC Topology Summary Slow, moderate cost.Up to 24-bit Up to bits < 100ksps < 10MSPS Delta-Sigma Up to 16-bit< 200MspsPipeline Fast, expensive, large power requirements. Up to 10-bit< 500MspsFlash Simple operation, low cost, low power. Up to 18-bit< 5MspsSAR Comments Resolution F Conversion ADC Topology Fast, expensive, large power requirements. 6

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D/A Converter –R-2R –String –Current Steering

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TI DAC Technologies Settling Time- s Current Steering Resistor String & R-2RR-2R Converter Resolution Current Technology High Speed Video and Communication Update rate (MSPS) Typically 1 Output but a few 2 Output Current out Industrial Settling Time (µs) Number of Out put DACs Resistor String – Inexpensive R-2R – More accurate -Trimmed at final test Typically Voltage out MDACs (dig control gain/atten, Waveform gen.) Instrumentation and Measurement Typically for Calibration

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R-2R Architecture + - 2R RRRRRRR R LSBMSB V R E F ( V OUT ) ANALOG OUTPUT + small. Only 2*N resistors required - tight resistor matching required - not inherently monotonic

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Resistor String DAC Architecture = V REF ( b i /2 i )

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Typical Block Diagrams of a Resistor String DAC

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I OUT 2 N -1 Current Sources Switches determined by digital input Current Steering DACs III

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Precision DAC Product Strategy Expensive High Accuracy Low Cost High Accuracy Great AC Specifications Small Packages High Channel Counts Single and Dual Supply Output Ranges More BACK Low Cost Limited Accuracy

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INL (LSB) Settling Time (µs) HPA07 Current Steering typically settles to 0.1% Precision DACs (R-2R and String) to.003% DAC Architecture Positioning * INL is at the 16-bit level Higher Power Consumption BACK More

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Data Converter Specifications

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Evaluating the ADC (Datasheet) Key Performance Characteristics DC –Offset error –Gain error –Differential linearity –Integral linearity AC –SNR –THD –SFDR Others

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N = Resolution of ADC 1 LSB = V FULLSCALE(nom.) 2 N N = LSB ± 5 V input rangemVmVmV V V V 1 LSB V input rangemVmVmV V V V 1 LSB V input rangemVmV V V V V How Large is an LSB ?

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Resolution vs. Accuracy: 4 Good Accuracy Poor Resolution Poor Accuracy Poor Resolution Poor Accuracy Good Resolution Good Accuracy Good Resolution

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AC Specs SNR (Signal-to-Noise Ratio) – RMS value representing the ratio of the amplitude of the desired signal to noise power below one half the sampling frequency. Measure of the strength of a signal to background noise. Contributes to the overall dynamic performance of the device at higher frequencies and affects the linearity at those frequencies. In the audio world, a low signal-to-noise ratio means the device has lots of hiss and static, while a high rating means clear-sounding audio. THD (Total Harmonic Distortion) – The ratio of the sum of the powers of all harmonic frequencies above the fundamental frequency to the power of the fundamental frequency. THD is usually expressed in dB. ENOB (Effective Number Of Bits) - The number of bits achieved in a real system. Is another way of specifying the SNR. ENOB = (SNR-1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits. SFDR (Spurious Free Dynamic Range) - The headroom available in an FFT plot. It is the distance in dB between the fundamental input and the worse spur. Fundamental Signal SFDR First Harmonic Second Harmonic Average Noise Floor

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DC errors Gain Error – The gain error is the difference between the ideal gain between zero and full scale on the transfer function and the actual gain after the offset error has been corrected to zero. This error represents a difference in the slope of the actual and ideal transfer functions and as such corresponds to the same percentage error in each step. This error can also usually be adjusted to zero by trimming Offset Error Ideal Transfer Function Actual Transfer Function Ideal Full Scale Range Actual Full Scale Range Offset Error – The offset error is the difference between the nominal and actual offset points. It is the difference in voltage between the first ideal code transition and the actual code transition of the ADC. This error affects all codes by the same amount and can usually be compensated for by a trimming process. If trimming is not possible, this error is referred to as the zero-scale error. Analog Input Voltage Digital Output code

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DC Specs DNL (Differential Nonlinearity Error) – (or simply differential linearity) The differential nonlinearity error is the difference between an actual step width (for an ADC) or step height (for a DAC) and the ideal value of 1 LSB (Least Significant Bit). If the DNL exceeds 1 LSB, the magnitude of the output gets smaller for an increase in the magnitude of the input. In an ADC there is also a possibility that there can be missing codes (if DNL < -1LSB) i.e. one or more of the possible 2 n binary codes are never output. INL (Integral Nonlinearity Error) - (or simply linearity error) The deviation of the values on the actual transfer function from the ideal transfer function once the gain and offset errors have been nullified. The summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the INL at that step. The unit for INL is LSB Ideal Transfer Function Actual Transfer Function Analog Input Voltage Digital Output code < 1LSB DNL > 1LSB DNL INL < 0

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Major DNL Errors Input Voltage ADC Missing Code

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LOST??? Different Datasheets list specs in different terminologies –INL in LSB, mV, %, PPM –Power in mW, V, I –Gain error/drift in %FSR, μV

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The Relevancy … LSBmV%PPM LSB* LSBX(2) [1].V ref X100 2 N LSB X N LSB X N mV mV X 2 N. (2) [1].V ref 100 * mV. (2) [1] V ref mV X 10 4 (2) [1].V ref % % X 2 N 100 % X (2) [1].V ref * % X 10 4 PPM PPM X 2 N 10 4 PPM X (2) [1].V ref 100 PPM 10 4 * [1] The factor 2 in brackets is to be used for a bipolar device. Cheat Book Power (W) = V in (V) X I oper (A)

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Output Code Input Voltage Ideal transfer characteristic Actual transfer characteristic ADC Offset Errors 10

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Output Code Input Voltage ADC Gain Errors 11

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Output Code Input Voltage ADC INL Errors 13

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Output Code Input Voltage ADC DNL Errors 12

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Output Code Input Voltage DNL Major Errors Output Voltage Input Code ADC Missing Code DAC Non-monotonic

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Dynamic Specifications Amplitude (dB) k2k3k4k5k6k7k8k9k10k Frequency - Hz Fundamental F H2H3H4H5H6H7H8H9 Harmonics 14-30

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Spurious Free Dynamic Range (SFDR) k2k3k4k5k6k7k8k9k10k Frequency / Hz Fundamental F SFDR Amplitude (dB) 14-32

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Amplitude (dB) 01k2k3k4k5k6k7k8k9k10k Frequency / Hz f 2 - f 1 2f 1 - f 2 f1f1 f2f2 2f 2 - f 1 f 1 + f 2 Intermodulation Distortion, IMD 14-33

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Measuring Noise RMS noise –Usually calculated from standard deviation of a series of samples –Used to calculate ENOB –Does not depend on noise type Peak-to-peak noise –Gives display resolution –Estimates typically assume that the noise is Gaussian

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Measuring Noise Calculating RMS noise Variance of a set of N samples: Standard deviation: Effective number of bits (if samples are ADC codes):

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Measuring Noise Peak-to-peak noise For Gaussian noise, > 99.9% of samples occur in the interval: Then our rule of thumb is: Peak-to-peak noise = 6.6 * RMS noise

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Signal to Noise Ratio (SNR) SNR = V SIN V N N is number of bits of resolution Each extra bit provides approximately 6 dB improvement in the SNR ! Effective Number Of Bits (ENOB): SNR(dB) = 6.02 N Quantization Noise +Q/2 -Q/2 Q ENOB = (SNR + D)(dB) FS0.5 FS Analog Input Voltage Digital Output Code Q 14-29

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Definition of "NOISE-FREE" code resolution Effective resolution =log 2 Full scale range RMS noise bits Noise-free Code resolution =log 2 Full scale range P-P noise P-Pnoise = 6.6 × RMS noise (most commonly used ratio) = effective resolution – 2.72 bits

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Typical output RMS NOISE in uV and effective resolution in bits Device (Semiconductor, Resistor) Noise Dominates at the Lower Frequencies (< 60 Hz notch) Quantization Noise Dominates at the Higher Frequencies

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The Aperture Error is less than 1 LSB, if: In a 12-bit system with a maximum signal frequency of 20 MHz, the Aperture- Jitter has to be less than 3.8 ps ! Aperture-Jitter (Sampling Uncertainty) t A V VPVP -V P TATA t A v V+ v

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Maximum Signal Frequency (MHz) * Equivalent converter SNR SNR(dB) *14 Bit *12 Bit *16 Bit 0.1 ps 0.3 ps 1 ps 3 ps 10 ps Jitter Limits

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–What is meant by 4 SE or 4 Diff? –What is meant by 3x2 Diff? Number of Input Channels Multiplexer ADC Multiplexer ADC

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Number of Input Channels Single Ended (SE) vs Differential (Diff) SE: –Referenced to ground –Grounds may not be the same across causing a noisier environment Diff: –Full-scale Range –Wider code steps –More accurate A in A in + A in -

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ADC Interface Solutions Principle Configuration Choices Single-Ended Input Differential Input ADC Input + fs Vcm - fs Vcm IN + fs/2 Vcm -fs/2 + fs/2 Vcm -fs/2 Requires full input swing from +fs to –fs 2x the swing compared to differential Input signal at IN typically requires a common-mode voltage for bias Input IN\ also requires a Vcm for correct dc-bias Combined Differential inputs result in full-scale input of +fs to –fs Each input only requires 0.5x the swing compared to single-ended Both inputs require a Vcm for correct dc-bias

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Typical SPI Interface 43

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I 2 C Interface DSPs 48

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Digital Signal Processor CLK R/W GPO GPI D[15..0] CLK ADS8322 D[15..0] CONVST BUSY CSGPO RD decoder A[19:0] Digital Signal Processor CLK R/W GPO INT CLK ADS8322 CONVST BUSY CSGPO RD logic A[19:0] D[15..0] logic Parallel Digital Signal Processor Figure 1 Figure 2 46

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Pseudo-Differential Mode ADCs ADCDAC AIN(+) AIN(-) +/- 200mV Maximum

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Pseudo-Differential Mode ADCs AIN(-) AIN(+) DAC OUTPUT

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Digital Change Delay Time t Glitch Settling Time, t s Final Value Error Band Analog Output (V) Settling time of a DAC

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Monotonicity A DAC is monotonic if its output either increases or remains constant as the digital input increases, with the result that the output will always be a single-valued function of the input.

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Glitch Improvement Main Cause of Glitch –Charge in the switch causes node voltage to change temporarily –More number of switches toggling when code changes – more glitch!! TSMC products uses Row- Column decoding (see next slide) – 30~40 switches toggling at any code change HPA07 products uses single decoder – maximum of two switches toggling at any time a + - V FB V IN V OUT R fb R t Charge Q gets split

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Comparison of A/D and D/A key Specifications A/DD/A Gain ErrorError in slope of transfer curve. Same Offset ErrorInput which causes the first bit transition to occur (ideal is ½ lsb). Output which occurs for input code which should produce zero output. Linearity errorDeviation of code midpoints from straight line. Deviation of analog output from straight line. Differential Nonlinearity Difference between actual width of code and ideal code (1 lsb). Difference between actual output increments and ideal (1 lsb) steps.

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ADC Nomenclature TI ADCs - TLC/TLVxxxx 0 or Blank 8-Bit 1 10-Bit 2 12-Bit 3 14-Bit 4 16-Bit 7 4½ Digit TLC: 5V TLV: 3V HS ADCs Not Included ADS51xx ADS52xx ADS54xx ADS55xx ADS8xx THS14xx THS12xx THS10xx BB ADCs & Future - ADS1xxx Delta-Sigma ADCs (except ADS1286 SAR) ADS1xxx: 12-Bit ADS11xx: 16-Bit ADS121x: 24-Bit, Integrated ADS122x: 24-Bit, Low Power ADS123x: 24-Bit Weight ADS125x: 24-Bit Programmable ADS127x: 24-Bit Fast AC/DC ADS16xx: 16-/18-Bit Wide Bandwidth - ADS78xx/ADS8xxx SAR/Nyquist ADCs ADS78xx: 8-/10-/12-/14-/16-Bit <1MSPS ADS83xx: 16-/18-Bit <1MSPS ADS84xx: 16-/18-Bit >1MSPS ADS85xx: 12-/16-Bit +/-10V - THS10xxx/12xx, TLV12xx/15xx High-speed (<10 MSPS) All Future DAP ADCs Will Have ADS Prefix!

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DAC Nomenclature TI 8-/10-/12-Bit DACs - TLC/TLV56xx TLC: 5 V TLV: 3 V High Speed CMOS DACs (Update Rate > 40MSPS) DAC56xx DAC9xx DAC29xx THS56xx Delta Sigma DACs DAC1xxx: 14/16-Bit Burr-Brown and Newer TI DACs - DACx5xx String DACs (0 to +5 V) DAC55xx: 8-Bit, I 2 C, Unipolar DAC65xx: 10-Bit, I 2 C, Unipolar DAC751x: 12-Bit, SPI, Unipolar DAC754x: 12-Bit, Parallel, Bipolar DAC755x: Enhanced 12-Bit, SPI, Unipolar DAC757x: 12-bit, I 2 C, Unipolar DAC85xx 16-bit, Serial or Parallel, Unipolar or Bipolar - DAC76xx R-2R DACs (0 to +2.5 V & +/-2.5 V) DAC76xx: 12-/16-Bit, SPI or Parallel, Bipolar - DAC77xx R-2R High-voltage DACs (0 to +10 V & +/-10 V) DAC77xx: 12-/16-Bit, SPI or Parallel, Bipolar - DACx8xx R-2R Multiplying DACs. 2 nd Source to ADI/LTC DAC78xx: 12-bit, SPI or Parallel DAC880x: 14-Bit, SPI or Parallel DAC881x: 16-Bit, SPI DAC882x: 16-Bit, Parallel - DAC883x: R2R DAC 16-Bit, SPI, Low Power, Best INL/DNL

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