# Basic Knowledge of Data Converters

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Basic Knowledge of Data Converters

Agenda Data Converter Overview ADC/DAC Basics
Sampling Theory ADC Architectures SAR Delta-Sigma Pipeline Flash DAC Architectures R-2R String Data Converter Specifications / Test (how to get them from DATASHEET) DC Spec. AC Spec. ADC/DAC Nomenclature

What is ADC Analog to Digital

What is DAC Digital to Analog

Delta-Sigma SAR Pipeline Flash DAC Architectures R-2R String

Basic ADC Theory Analog signal is sampled
The sampled analog signal is compared to one or more reference voltages The result of the comparison is converted by digital logic to a binary number.

SHANNON’S information theorem NYQUIST’S Criteria
An analog signal with a Bandwidth of fa must be sampled at a rate fs>2fa in order to avoid the loss of information. The Signal Bandwidth may extend from DC to fa (Baseband Sampling) or from f1 to f2, where fa = f2-f1 (Undersampling, or Super-Nyquist). Nyquist: If fs<2fa, then a phenomenon called aliasing will occur. Aliasing is used to advantage in undersampling applications

NYQUIST'S THEOREM: fs-f1 > f1  fs > 2 ´ f1
Sampling Theory Input Waveform f(t) t t1 t2 t3 t4 Sampling Function Unit Pulses h(t) t T Sampled Output t g(t) t1 t2 t3 t4 f(t4) f(t3) f(t2) f(t1) X = Fourier Transform Input Spectrum F(f) f1 f Sampling Spectrum Sampled Spectrum G(f) f1 f fs fs+f1 2fs-f1 H(f) Nyquist region = * fs = 1/T 2fs f * NYQUIST'S THEOREM: fs-f1 > f1  fs > 2 ´ f1 14-8

Oversampling

Why Oversample? TO MOVE ALIASING FREQUENCY FURTHER FROM THE DESIRED SIGNAL. TO RELIEVE ANTIALIASING AND RECONSTRUCTION FILTER REQUIREMENTS COST COMPLEXITY RESPONSE TO ALLOW FOR LOWER APPARANT INPUT NOISE BY FILTERING IN THE DIGITAL DOMAIN. TO ALLOW FOR LOWER APPARANT INPUT NOISE BY SPREADING THE QUANTIZING NOISE OVER A WIDER BANDWIDTH.

OUTPUT SIGNAL RMS QUANTIZATION NOISE = q/ 12 f s 2

Effects of oversampling on Quantization Noise

Analog signal fa sampled @ fs has images (aliases) at |±Kfs ±fa|, K = 1, 2, 3, ...

Effect of oversampling on filter requirement

Analog filter requirement for fo = 10MHz: fS = 30MSPS AND fS = 60MSPS

Undersamplinig

Why Undersample? The AC bandwidth of the “analog portion” of an ADC is usually wider than the maximum sample rate. Nyquist says that the BANDWIDTH not the FREQUENCY of the signal must be ½ sampling rate. You can process the spectrum at harmonics of the sample rate as well

Undersampling

Minimum sampling rate as a function of the ratio of the highest frequency to the total signal bandwidth 4.0 f s B = SIGNAL BANDWIDTH B f = MAXIMUM SIGNAL FREQUENCY MAX 3.5 f = MINIMUM REQUIRED SAMPLING RATE s 3.0 2.5 2.0 4 1 5 2 3 B f MAX

Intermediate Frequency (IF) signal at 72
Intermediate Frequency (IF) signal at 72.5MHz (±2MHz) is aliased between DC and 5MHz f s = MHz 7f s = MHz dc f s 2f s 3f s 4f s 5f s 6f s 7f s 10 20 30 40 50 60 70 BASEBAND SIGNAL: ALIAS: 72.5 ± 2 MHz dc TO 5 MHz s f = MSPS

Anti-aliasing filter for undersampling
DR 0.5 f S s - 1 Bandpass filter specifications STOPBAND ATTENUATION = TRANSITION BAND: 2 TO 2f CORNER FREQUENCIES: , 1.5 IMAGE IG NA LS O F I NT E RE ST f c f 1 TO f s - f 1

Quantization Error Analog signals are continuous
Digital signals have discrete values A digital word that is converted to an analog signal will always contain errors Quantization Error or Noise is dependent on the number of bits used in the conversion In the process of converting from an analog to a digital signal, the resolution of the conversion is governed by the number of bits used in the converter. As a result, a theoretical error corresponding to the discrepancy between the analog signal and the smallest digital value is generated. This error is defined as a “Quantization Noise” error. The level of quantization noise, NQ, can be calculated using the following equation: The value of the least significant bit or VLSB is given by: Where VFSR is the full scale output range of the converter and N is the number of bits used in the conversion. The Dynamic Range (DR) and/or Signal-to-Noise Ratio (SNR) is also an important measure of a converter’s accuracy. These two performance parameters are calculated from the following equation: NQ= •VLSB2 1 12 VLSB= VFSR N-1 DR=6.02•N+1.76{dB}

Quantization Why would the quantization error be considered “noise”? The graph above shows a transfer function for a three-bit converter. Because the converter can only represent certain values, it deviates from the ideal straight line, but does so in a repeatable pattern. The error varies from +/ LSB, as shown in the lower graph. If your signal were varying across the full input range, then this error signal would be present as well – and anything that isn’t signal in your signal is by definition noise. Thus, this error is correctly identified as quantization noise.

Data Converters’ Architectures
ADCs Delta Sigma SAR Pipeline Flash DAC R-2R String Customers Talk Architecture??? Should you be scared - NO Can you handle it - TRY Just know the key characteristics and you have just focused in on your device selection

- SAR - Pipeline - Flash - Delta Sigma
A/D Converter - SAR - Pipeline - Flash - Delta Sigma

ADC Architectures: Speed, Resolution, and Latency Analogy
Delta Sigma 16 to 24 bits of resolution Typically Slow 10SPS to 105kSPS Long Latency If I was a camera I would have my aperture open longer SAR 8 to 18 bits of resolution ~50kSPS to 4MSPS No latency If I was a camera I would be have fast shutter speed Pipeline 8 to 14 bits of resolution Up to over 300 MSPS Some clock cycle latency I want to be a video camera when I grow up Flash 8 to 10 bits of resolution Up to over 1 GSPS no latency I just want to be FLASH

TI Analog to Digital Families
500 k 100 k 10 k 1 k Advantages Higher Speeds Higher Bandwidth Disadvantages Lower Resolution Pipeline Delay/Data Latency More power Pipeline Delta Sigma Advantages High Resolution Low cost Low Power typically High Stability (averages and filters out noise) Disadvantages High Latency Low Speed typically SAR Advantages No Latency (happens immediately) High Resolution and Accuracy (<=18-bits) Typically Low Power Easy to Use and Multiplex Disadvantages Typically sample Rates Limited to Approximately 4 MHz Speed: Sample Rate in SPS Delta Sigma Accuracy (Resolution in bit)

ADC – Successive Approximation Register (SAR) Architecture
Ref VIN MSB LSB Data Out fS + - S/H Clock SAR and Control Logic D/A Converter An “n” bit SAR converter takes n cycles to complete a conversion. From most to least significant bit (MSB to LSB) simple compare functions are done and, when a bit is a 1, that amount of voltage is subtracted from the input signal. SAR’s are workhorse converters… easy to use… simple to understand… but are limited in both resolution and speed. TI has MANY SAR ADCs. MSB LSB FS FS: Full Scale 2 Modern SARs use a C-DAC to successively compare bit combinations, set or clear the corresponding bits in a data register, and they also tend to have an integrated sample/hold function. A typical SAR conversion cycle has two phases; a sampling phase and a conversion phase. During the sampling phase, the analog input signal is allowed to charge the ADC’s Sample-and-Hold (S/H) capacitor to a level proportional to the analog input. Conversion begins immediately following the sampling phase. Conversion successively compares the unknown value of the charge stored in the S/H capacitor to known fractions of charge. After each comparison, logic on the ADC determines if the unknown charge is greater or smaller than the known fractional charge.The process will be like this x >1/2 FS ? - Y - set the corresponding bit x >3/4 FS ? - N - clear the corresponding bit x >7/8 FS ? - Y - set the corresponding bit etc At the end of the process the data register will contain a binary value proportional to the value initially placed on the S/H capacitor. The user reads this value out as converted data.

Pipeline converters are another high speed architecture. Several lower resolution converters are put together to result in a fast conversion time. Generally lower power and lower cost than Flash converters, the main disadvantage of a Pipeline converter is that it takes as many clock cycles as there are stages to output the data resulting in latency. STAGE 1 STAGE N ANALOG INPUT Sample Hold Amplifier Sample Hold Amplifier + S + S ADC - - SAMPLE HOLD AMPLIFIER ADC DAC ADC DAC REGISTER REGISTER TI has many Pipeline converters! PARALLEL DIGITAL OUTPUT

Latency SARs have none….OK, just a little
ADS7881 12 bits 4MSPS Snapshot Acquisition Time Conversion Time = 150ηs Aperture delay = 2ηs If it was a 12 bit pipeline with 2 bits/stage, you would need: Target Applications Handheld Instrumentation DVMs Medical Equipment Weigh scales Easy to build synchronous multi-channel systems using multiple ADS1244s. ADS1245: includes an Input Buffer. Input impedance is 30GOhm, minimizing leakage current errors when using high-impedance transducers. The ADS1245 will be released in Q3 2003 150 ηs Conv t Delay = 6.6MSPS X 6 clock cycle delay = 40MSPS

Pipeline A/D Converter Timing and Data Latency
Sample Points S4 S5 S8 S1 S9 Analog Input S2 S3 S6 S7 Track Hold Clock Data Latency, 6.5 clock cycles Track Hold Internal S/H To obtain the best performance from pipelined A/D converters the designer needs to make careful considerations about the timing and the clock source. This is basically true for all high speed A/D converter architectures. Clock jitter can introduce a significant error and needs to be kept low to avoid a degradation of the resolution. With pipeline A/D converters, the rising and the falling clock edge are used to initiate certain operations. Each converter stage in the pipeline will be sampling during one phase and amplifying in the other phase. The internal S/H clock applied to each sub-converter is offset by 180° phase from the previous stage clock signal with the result that alternate stages will perform the same operation (concurrent operation). The duty cycle of the external clock should be held at 50% with a low jitter of less than 3.5ps (for the 40MHz ADS8XX) especially when digitizing a high frequency input signal and operating the maximum sample rate. A deviation from the 50% duty cycle will effectively shorten some of the interstage allowed settling times, thus degrading the SNR and DNL performance. The first valid digital data of the pipeline architecture will have an associated delay before it becomes available at the bus. This delay is called “Data Latency” and is dependent on the number of internal converter stages . For example, the ADS8XX has a data latency of 6.5 clocks. n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Output Data n-7 n-6 n-5 n-4 n-3 n-2 n-1 n

Pipeline A/D Converter Signal Encoding: SAR vs. Pipeline
SAR: Serial Encoding Sample #1 MSB B2 B3 B4 B5 B6 B7 LSB Conversion Time Pipeline: Parallel Encoding Sample #1 MSB B2 B3 B4 B5 B6 B7 LSB Conversion Time Sample #2 MSB B2 B3 B4 B5 B6 B7 LSB The main advantage of pipeline ADCs is that they can provide a high throughput rate with moderate IC design complexity and low power consumption. This is because of the concurrent operation of the n-stages. The associated “data latency” is not a limitation in many applications. Two main clock phases are required per conversion; because the pipeline ADC uses flash converters. Therefore the maximum throughput rate can be high. After the initial data latency time, the data representing each succeeding sample is output with every following clock pulse. Sample #3 MSB B2 B3 B4 B5 B6 B7 LSB

And Now for something completely different
Delta Sigma’s

Delta-Sigma Overview What is a delta-sigma ADC?
A 1-bit converter that uses oversampling (can be multi-bit) “Delta” = comparison with 1-bit DAC “Sigma” = integration of the Delta measurement What is the advantage of delta-sigma? Essentially digital parts which result in low cost High resolution What are the disadvantages? Limited frequency response Most effective with continuous inputs Latency A delta-sigma ADC is a one-bit converter that uses oversampling implemented with a 1-bit ADC, a 1- bit DAC and an integrator to resolve the analog voltage into a digital equivalent. The basic conversion element of any converter must be more accurate than the required measurement. A 1-bit ADC is as linear as we can make because there are no differential non- linearities. The delta-sigma converter lends itself to low power supply or non-analog processes because the 1-bit converter can be made in any process at low supply voltages. Furthermore, a 1-bit ADC outputs a stream of ones and zeros which requires lots of data shifting, digital filtering, and logic, thus the 1- bit converter can be made efficiently from a digital process. The benefit of delta-sigma is that it moves most of the process into the digital domain. The analog components use a single comparator, integrator and 1-bit DAC. Since the 1-bit DAC has only two outputs, it is linear across the voltage range. 3

S D Converters – Functional Block Diagram
Analog Input 1-bit wide n-bits Digital Output Filter Modulator PGA Advantages: Minimum analog components Integrates easily with digital logic Oversampling reduces inband noise Disadvantages: Speed limited to upper audio range

Delta-Sigma A/D Converters
The diagram in this slide shows the basic block diagram for a delta-sigma ADC. The basic idea behind a delta-sigma converter is to sample an input signal in a very crude fashion, but at a very high rate. A complete delta-sigma ADC then takes this crudely sampled, noisy, but very fast signal and converts it into a clean signal at a much lower rate. While most converters have only one sample rate, delta-sigma converters actually have two: the input sampling rate and the output data rate. Usually the input sampling rate is called simply “sampling rate”, and the output data rate is called “data rate”. The data rate is the rate at which samples are output from the converter. For most kinds of ADCs, the data rate and sampling rate are the same; one complete code is converted for each input sample. For a delta-sigma, many input samples are taken to produce one output code. In the following slides, bear in mind that we are sampling the signal at a high rate, but generating data at a much lower rate. To do this, delta-sigma converters use an unusual kind of input signal quantizer (A/D converter) running at a very high sampling rate to obtain a high-quality result at a lower data rate. This unusual quantizer is called a delta-sigma modulator. In the diagram, we’ve shown an analog input signal being converted to the modulator’s output, which is a pulse waveform. Like all quantizers, the delta-sigma modulator takes an input and produces a noisy output. Unlike most quantizers, the delta-sigma modulator’s quantization noise is very, very high. Also unlike most quantizers, the spectrum of this noise isn’t flat. We’ll see how this helps us in the next several slides. Following the modulator is a digital decimating filter. This device filters and resamples the stream of 1-bit samples coming from the modulator. Resampling is the process of taking samples of a digital signal. We will see what this accomplishes in later slides.

Delta-Sigma A/D Signal Path
You are here In the slides that follow, we take you on a tour through a theoretical delta-sigma ADC’s signal path. We show some extra steps to help clarify what’s going on in the device. In particular, real delta-sigma ADCs combine the digital filter and decimator into a single unit, as noted previously, but we show what the undecimated filtered modulator output would look like if it really existed in the converter’s internals. At each stop in our “tour”, we’ll highlight on the “map” where we are before taking a close look at the signal at that point. We begin at the converter’s input, which is circled in red above.

Delta-Sigma A/D Signal Path
TIME DOMAIN FREQUENCY DOMAIN The signal starts off as an analog signal – typically a time-varying voltage. In the graph on the left, we’ve shown a single cycle of a sine wave. In the frequency domain, a continuous sine wave appears (on the positive side; we won’t discuss negative frequencies) as a straight line. This is shown in the graph on the right.

Delta-Sigma A/D Signal Path
Next, we’ll look at the output of the modulator.

Delta-Sigma A/D Signal Path
TIME DOMAIN FREQUENCY DOMAIN Here is what the signal looks like after the modulator has worked its magic. Doesn’t look much like magic in the time domain, does it? Far from it - it looks positively awful! Certainly the output looks nothing like the original signal. To see why the modulator really is a useful device, look at its output in the frequency domain. Compare the input signal on the previous slide with the output signal on this slide. Those pulses in the time domain show up as shaped noise in the frequency domain. And yes, the sine wave is still there! It’s just obscured by all that noise. That noise is a problem, of course: we certainly don’t want it in the final output of the converter. To get rid of it, we need a low-pass filter. In a delta-sigma converter, we use a digital low-pass filter to get rid of the noise.

Delta-Sigma A/D Signal Path
TIME DOMAIN FREQUENCY DOMAIN We want to pass the modulator’s output to a digital filter, but a delta-sigma modulator is an analog component. Fortunately, its output is very easy to convert to digital codes. The above diagram shows the same pulse train as a two-level discrete-time signal. This will be the filter’s input. Since the modulator runs at a certain sampling frequency, the pulses are really samples, and we can treat them as such. Note: Practical delta-sigmas usually treat a 1 as 80% of positive full-scale and 0 as 80% of negative full-scale. This keeps the converter from saturating at the input limits.

Delta-Sigma A/D Signal Path
We now come to a point in the tour that doesn’t actually correspond to a real point in the vast majority of delta-sigma ADCs: the output of the digital filter prior to decimation. I’ve chosen to show this for clarity. Remember, though, that almost no delta- sigma actually has a high-speed smoothed-out sine wave like this internally.

Delta-Sigma A/D Signal Path
TIME DOMAIN FREQUENCY DOMAIN Here is what the signal looks like after the digital filter has cleaned it up. Our signal looks nice again! In the time domain, it rather looks like the digital filter is really the “magic” part of a delta- sigma converter; it turned that horrible pulse-train mutilation of the input back into something resembling the original. But in the frequency domain, we can see that it’s not doing anything all that special. It simply low-pass filtered the signal, and in so doing, it attenuated the quantization noise put in by the modulator. With the quantization noise gone, our signal re-emerges in the time domain. Since the filter is digital, its output is in the form of digital codes. We now have a digital version of the input, but there’s one problem: it isn’t at the output data rate, but at the input sampling rate. Because we have just low-pass filtered the signal, however, there is hardly any signal above the filter’s break frequency; the only thing left is noise, and hopefully not much of that. So, while it might appear that we have a lot of high-quality samples at the high sampling rate, most of those samples aren’t real – they are simply interpolations between real samples of the input. We could certainly make a converter deliver every one of these samples, but this has several disadvantages: * Such a converter would require a very fast data interface – in most delta-sigmas, the data rate is hundreds of times lower than the sampling rate. * The receiver of the data would have to deal with all of the data, which is impractical for some applications. * The filter would have somewhat more complex circuitry, and it would use more power. * Most of these samples, being mere interpolations between real sample points, deliver no useful information. Clearly we have too many samples. What to do? We must decimate the signal.

Delta-Sigma A/D Signal Path
Now we come to a point that does exist in a real delta-sigma: the output.

Delta-Sigma A/D Signal Path
TIME DOMAIN FREQUENCY DOMAIN Decimation is the process of reducing a digital signal’s sampling rate. The way to do this is amazingly simple: discard some of the samples. The result has fewer samples than the original, as shown above. This may seem a bit distressing at first. In the previous slide, we had a beautiful sine-wave, well defined with a large number of samples; yet we threw a large number of those samples away, and are left with what appears to be a mere skeleton of the original. But remember that most of those samples weren’t “real” – you can think of them as intermediate samples, rather like works-in-progress, from the filter. In fact, according to the Nyquist theorem, our new “skeletal” version of the signal has exactly the same informational content as the previous waveform, but now it is at a manageable sample rate – in fact, it is at the data rate, which is the rate we signed up for to begin with. Bear in mind also that we haven’t actually lost any information in this process; we have only discarded the portion of the spectrum that could never have any information in it anyway, because the signal was passed through a low-pass filter. In the frequency domain, this decimation creates aliases, just as “real” sampling does. (Actually, we’ve just compressed our band – the aliases were there before, but we “zoomed out” on the spectrum. See a DSP text for details.) But since our sampling rate is lower, we only “see” the frequencies from 0 to the data rate, which is marked on the diagram as “Fd”. The sampling rate – i.e., the rate at which the modulator sampled the signal – is “Fs”. We have already mentioned that the filter and decimator are usually implemented as a single unit. The reason is that when we follow a filter with a decimator, we are throwing samples away. It turns out that we can, instead of calculating a bunch of samples that we know we won’t use, simply refrain from calculating them in the first place. A filter that only calculates some of its output samples is called a decimating filter. This is the kind of filter used in a delta-sigma A/D converter.

Delta-Sigma A/D Signal Path
OUTPUT OF DECIMATING FILTER SIGNAL FROM MODULATOR This slide shows how the filter section of a delta-sigma really works. The high-sample-rate sine wave never really appears in a practical delta-sigma. We have already mentioned that the filter and decimator are usually implemented as a single unit. The reason is that when we follow a filter with a decimator, we are throwing samples away. It turns out that we can, instead of calculating a bunch of samples that we know we won’t use, simply refrain from calculating them in the first place. A filter that only calculates some of its output samples is called a decimating filter. This is the kind of filter used in a delta-sigma A/D converter. Using a decimating filter is much more efficient than calculating a large number of codes that will go unused. In a real delta-sigma, the high-sampling-rate sine wave shown in the preceding slides never actually exists. One extremely simple way to make a decimating filter is to average groups of input samples together. This is very easy to demonstrate. Suppose the oversampling rate is 8, and the modulator sends out the following samples: 0, 1, 1, 0, 1, 0, 1, 1 The average of these eight modulator samples is ( )/8 = 5/8. We have just calculated one output of a decimation filter. If we were to take the average of the modulator’s analog input over the same period of time, we would arrive at the same result. Averaging is really a form of digital filtering. A moving average, where an average is taken repeatedly over a number of past inputs, is a non-decimating filter, since one output sample is generated for each input sample. A normal average, where blocks of input samples are averaged to produce single output samples, is equivalent to following a moving average by decimation. Averaging certainly isn’t the only way to perform digital filtering, but perhaps surprisingly, it’s one of the most common techniques used in delta-sigma converters. Almost all delta-sigma converters incorporate a class of averaging filters called sinc filters, named for their frequency response. Many delta-sigma devices, especially audio devices, use other filters in conjunction with sinc filters; low-speed industrial delta-sigma ADCs usually use only a sinc filter. DECIMATING FILTER

Oversampling, digital filter, NOISE SHAPING, AND DECIMATION
fs 2 Kfs DIGITAL FILTER REMOVED NOISE QUANTIZATION NOISE = q / 12 q = 1 LSB ADC DIGITAL FILTER SD MOD DEC Nyquist Operation Oversampling + Digital Filter + Decimation + Noise Shaping A B C Kfs

The Delta-Sigma Modulator
Signal input, X1 X3 + - To Digital Filter X2 X4 + - Difference Amp Integrator Comparator (1-bit ADC) VMax X5 1-bit DAC The delta-sigma modulator consists of a differential amplifier, an integrator, a comparator, and a 1-bit DAC. The input signal is subtracted from the 1-bit DAC signal, and the remainder is applied to the integrator input. When the system reaches steady state operation the integrator output signal is the sum of all the error voltages, and the integrator acting as a low-pass filter has lowered the noise content. One integrator yields –6dB noise suppression, so sometime several integrators are used to decrease the quantization noise in the passband. The integrator output signal is quantized using a 1-bit ADC (the comparator). The comparator output is a bit stream whose density of digital 1s is proportional to the ratio of the input signal to the reference signal. The DAC converts the comparator signal into a digital waveform which is compared with the input signal. 4

Delta-Sigma Modulator
Now, let us review the waveforms found in a simple delta- sigma modulator. The input signal, X1, is at 1/4 scale. The input signal minus the DAC output signal is a pulse train with one period low and three periods high. The integrator falls for one period and rises for three periods. The only way the integrator output can fall for three periods is if that output is below ground for three periods, and looking at the comparator output, (X4) we see that this has to be the case to achieve steady state operation. The comparator output is the serial bit stream that contains the data conversion. Each of the vertical lines represent where the comparator output is latched by the modulation clock. To analyze the operation, it is best to start with the output and see how it interacts with the input. The input voltage is 1/4 of Vmax range. We start with the output high, since the DAC follows the output it has an output of Vmax. The initial difference amp has Vmax/4 and Vmax which creates an output of -3/4 Vmax. As can be seen, negative voltage causes the integrator to have a strong negative slope.

Delta-Sigma Modulator
Averaging Filters Full-scale DC input levels 0V Delta-Sigma Modulator 1-bit data 1-bit data streams 1/2 full-scale input 1/4 full-scale input 3/4 full-scale input 0 Average 0 Average 1 Average 1 = = = 0.75 In order to see the action of the digital filter, first consider the case of a DC input level. The slide shows the values present on the 1-bit data stream for three values of the input level. As is clearly shown, the average value of the1-bit data represents the value of the input signal. In this case, 4 samples of the 1-bit data were averaged, but any number of samples could have been chosen. Higher numbers of sample averages improves the accuracy of the result. The filter used in a delta-sigma ADC is similar to a averaging filter. But as we will see in the next slide, averaging by itself will not work.

The Frequency Domain Power Frequency Signal amplitude
SNR = 6.02N dB ; (for an N-bit ADC Sine wave input) Quantization Noise Average noise floor (flat) Having looked at the effects of sampling and quantization noise in the time domain, the frequency domain of quantization is examined next. This slide shows a diagram of the FFT of the waveform from the previous slide. The signal being captured is a pure sine wave, which clearly shows up in a single frequency bin of the FFT. The FFT also shows a lot of random noise in all other bins, distributed flat across the frequency range from DC to FS/2. This is quantization error and is known as quantization noise. Remember that every sample taken of the input signal has a quantization error and that the magnitude of this error is random up to ±1/2 LSB. It is this random error, present on every sample, that generates the noise floor in the FFT. The noise floor shown does not consider the inherent shortcomings of the ADC. ADCs have error sources, but in this case, we are looking at a perfect ADC. Taking the RMS sum of all the frequency bins containing noise (i.e. all except the fundamental) and dividing this into the fundamental amplitude gives the signal-to-noise ratio (SNR). It can be shown that for an N-bit ADC, the SNR ratio is given by SNR = 6.02 N dB (for a full-scale sine wave input). This formula clearly shows that the obvious way to improve the SNR is to increase the number of bits in the ADC. Conversely, when the number of bits are increased, the reproduced input signal is more accurate. Delta-sigma ADCs take another approach. This is to use a 1-bit ADC and by using the techniques of oversampling, noise shaping and filtering, improve the accuracy. FS / 2 FS Frequency

Oversampling by K Times
Power SNR = 6.02N dB ; (for an N-bit ADC Sine wave input) Same total noise, but spread over more frequencies Average noise floor The total noise is independent of the oversampling; it stays constant. Sampling spreads the quantization noise over the sampled bandwidth. Oversampling increases the bandwidth considerably, hence it spreads the quantization noise over a wider bandwidth. The result is lower inband quantization noise, and this is the only noise that can’t be filtered out. In the previous example, the signal frequency was fairly close to the Nyquist frequency of FS/2. Here the affects of oversampling can be seen. The signal frequency is the same, but the sampling frequency has been increased by an oversampling ratio of k to kFS. Notice how this FFT shows that the noise floor has dropped. It is important to realize that the SNR is still the same as it was before as the formula on the previous slide made no reference to sampling frequency. The total amount of noise energy is still the same. But as it has just been spread over a wider frequency range, the noise level in each frequency bin has been reduced. k FS / 2 k FS Frequency

SNR = 6.02N + 1.76dB + 10 log(Fs/2*BW)
The Digital Filter Ideal digital filter response Oversampling by K times SNR = 6.02N dB + 10 log(Fs/2*BW) Power Noise removed by filter In the previous slide it was shown how oversampling spreads the noise over a wider bandwidth and hence reduces the level of the noise floor. Delta-sigma converters make use of this effect by following the 1-bit ADC with a digital filter. The effect of this filter is to restrict the noise bandwidth. Since most of the noise cannot now pass through the digital filter, the RMS noise (i.e. the RMS sum of the noise in those frequency bins that can pass) is reduced. This technique of spreading the noise over a wide frequency range, then filtering out most of the noise, is how a delta-sigma converter achieves a wide dynamic range from a low resolution ADC. BW k FS / 2 k FS Frequency

Noise-Shaped Spectrum
Signal Amplitude SNR = 6.02N dB Power The integrator serves as a highpass filter to the noise. The result is noise shaping The effect of the integrator in the delta-sigma modulator is shown here. The noise spectrum can be seen to rise as the frequency increases. Note that the total noise power i.e. the RMS sum of all the frequency bins has not changed. There is no less total noise than in the case of simply oversampling, but the distribution of the noise has changed. k FS / 2 k FS Frequency

1st order  Modulator Vin(t) Integrator D/A CLK Dout(t)

Filtering the Shaped Noise
Signal amplitude Digital filter response Power HF noise removed by the digital filter A digital filter is now applied to the noise shaped delta-sigma modulator. More noise is removed than in the simple oversampling case. The delta-sigma modulator just described is a first-order system and gives a 9-dB improvement in SNR for every doubling in sample rate. Compare this with a mere 3 dB achieved by oversampling alone. Using this architecture, it is now possible to implement a high-accuracy ADC from a single-bit delta-sigma modulator with a practical oversampling ratio. k FS / 2 k FS Frequency

The 2nd Order Delta-Sigma Modulator
INTEGRATOR INTEGRATOR 1-BIT ADC + + 1-BIT OUTPUT - - 1-bit DAC As we went through the last slide, I’m sure many of you were thinking to yourselves: “Sure, this first-order modulator is a great circuit; but I’ll bet it would be even better if it had two integrators instead of just one!” You weren’t? Well, if you had thought that, you’d have been right. Integrating twice, instead of just once, is a great way to lower the modulator’s in-band quantization noise. The technique has its limits, of course, but most delta-sigma modulators are higher-order, like the one shown above. The concept behind this trick is revealed in the transfer function. Now the noise term depends not just on the previous error, but on the previous two errors. Now the quantization noise is more strongly differentiated. The noise function is now shaped like one-quarter of sin^2(f). As mentioned before, we can add more loops to get higher and higher modulator orders. Each time we do, we get better noise – at the cost of higher power and more difficult design. MODULATOR OUTPUT SPECTRAL QUANTIZATION NOISE DENSITY

The Delta-Sigma Modulator
All that math is fine, but in this case, a picture says a great deal. Plotted above are the spectral noise densities for modulator orders 1 through 4, for a sampling frequency of 1kHz. The highest line is the one for the fourth-order modulator – it’s very, very noisy near the Nyquist frequency. But down in the baseband, where our signal is, it’s very quiet – quieter than any of the other modulators. The first-order modulator has a great deal more noise in the signal band, but much less across the entire spectrum.

The Delta-Sigma Modulator
Here is the same set of plots, but plotted from 0 to fs/128 instead of 0 to fs, which corresponds to the signal band for a decimation ratio of is a fairly common decimation ratio. (fs was chosen as 1000 for this example, but the graph looks the same no matter what fs is.) The lonely red line is for the first-order modulator. The other modulators are much quieter here in the signal band. For a given modulator order, there is a minimum achievable noise floor for a given decimation ratio. Higher-order modulators can achieve lower noise, but at the cost of added complexity and power consumption. Higher-order modulators also require stronger filtering, because their out-of-band noise is so much higher. 3rd-order modulators and up are also very difficult to design.

Sampling speed vs. ENOB Fd
Many delta-sigma converters have a programmable data rate. The data rate isn’t programmed directly, though – what’s adjusted is the decimation ratio. The decimation ratio is the ratio Fs/Fd, where Fs is the sampling frequency and Fd is the data rate. The decimation ratio is the number of times the modulator samples for each sample output. Values for decimation ratio range anywhere from 4 or 8 (ADS1605) to 32,768 (maximum for the ADS1256). Fs is usually derived from the converter’s master clock. Typically it is fixed, and Fd is varied. In this and the next slide, we show why changing Fd changes the converter’s ENOB. Consider the spectrum of the output of a delta-sigma modulator as shown in the slide. The modulator samples at Fs, and in so doing, adds quantization noise shaped as shown. Suppose we make the data rate some fraction of this, as shown above. The frequencies from 0 to Fd, which comprise the output, are the signal band. Note the level of the noise in the signal band. Since Fd is determined by the decimator, it depends on the decimation ratio DR, where DR=Fs/Fd.

< 5Msps Up to 18-bit Simple operation, low cost, low power. Delta-Sigma < 100ksps < 10MSPS Up to 24-bit Up to bits Slow, moderate cost. Flash < 500Msps Up to 10-bit Fast, expensive, large power requirements. Pipeline < 200Msps Up to 16-bit Fast, expensive, large power requirements. 6

D/A Converter R-2R String Current Steering

TI DAC Technologies Settling Time- s DS Resistor String & R-2R 20 16
Instrumentation and Measurement Typically for Calibration Industrial Settling Time (µs) Number of Out put DACs Resistor String – Inexpensive R-2R – More accurate -Trimmed at final test Typically Voltage out MDAC’s (dig control gain/atten, Waveform gen.) 20 DS Current Technology 16 High Speed Video and Communication Update rate (MSPS) Typically 1 Output but a few 2 Output Current out Resistor String & R-2R Converter Resolution Current Steering 12 8 1000 100 10 8 6 4 2 1 .05 .001 Settling Time- s

R-2R Architecture R R R R R R R R ANALOG OUTPUT - + ( VOUT ) 2R 2R 2R 2R 2R 2R 2R 2R 2R LSB MSB VR E F The multi-bit DAC is also referred to as R- 2R ladder and current steering. For each new update, internal current sources are turned on or off, based on the digital input word. The above figure illustrates a basic R-2R architecture. Starting at the least significant current source, each has a value twice that of the previous source, with the exact value being set by a ratio of two resistors. The outputs of all the current sources which are "on" are summed to produce the correct analog output. This is a relatively simple architecture to manufacture, assuming the resistors for each current source can be properly adjusted to the necessary precision. These resistors are usually thin- film and laser-trimmed to the final value. The classical R-2R topology has certain drawbacks, even when the resistors can be trimmed to a near-ideal value. This architecture is one which inherently assumes parallel data input. For the devices which have a serial interface, the multi-bit DAC uses a serial-to-parallel register internally before latching the data to the DAC. In either case, there is the possibility for data timing skews. These skews manifest themselves at the output as glitches. The glitch is most prevalent during the MSB transition, when bits are switching from to There is a brief moment in time when all bits are on or off. For example, the DAC switches might be briefly set to all ones (because the MSB switch is faster than the others). To some finite amount, this will occur for any given transition due to uncontrollable sizing errors in the devices and metal lines. If the time period is too long, then the output will begin to slew towards positive or minus full scale. If the time period is short enough, the output will not have time to change and the effect of the glitch will be inconsequential. + small. Only 2*N resistors required - tight resistor matching required - not inherently monotonic

Resistor String DAC Architecture
= VREF (bi/2i) This is a simple illustration of a 3-bit resistor string DAC. In this example, the digital input code is 101b which is decoded to 5/8 VREF. The output stage buffer is required to unload the passive elements, and convert the load current to a low-impedance voltage output. This can also provide amplification if necessary.

Typical Block Diagrams of a Resistor String DAC
In some string DACs, the output buffer is configurable, as shown in (a). Others have a fixed gain, such as a gain of 2, as shown in (b).

Switches determined by digital input
Current Steering DACs 2N-1 Current Sources I I I IOUT A Current Steering DAC is based on switched current sources. It has two current outputs, with one providing the complementary current of the other. The sum of the output currents is always constant. An array of switches, which is controlled by the digital input, directs the current of the sources to one of the two output rails. Like the resistor string architecture, current steering also guarantees monotonicity. And it allows much higher speeds, than designs with voltage outputs. Switches determined by digital input

Precision DAC Product Strategy
String DAC Topology Focus! Low Cost High Accuracy Great AC Specifications Small Packages High Channel Counts Single and Dual Supply Output Ranges Low Cost Limited Accuracy HPA07 Expensive High Accuracy R/2R DAC Topology BACK More

DAC Architecture Positioning
15 Current Steering typically settles to 0.1% Precision DACs (R-2R and String) to .003% HPA07 10 Settling Time (µs) Precision R-2R Precision String 5 Current Steering Higher Power Consumption 1 10 16 32 64 BACK * INL is at the 16-bit level INL (LSB) More

Data Converter Specifications

Key Performance Characteristics DC Offset error Gain error Differential linearity Integral linearity AC SNR THD SFDR Others

How Large is an LSB ? 1 LSB = VFULLSCALE(nom.) 2N
N = Resolution of ADC N = 1 LSB ± 5 V input range mV mV mV V mV mV 1 LSB + 5 V input range mV mV mV mV mV mV 1 LSB + 3 V input range mV mV mV mV mV mV Speaker: It stands for the same thing it does in DSP. It stands for least significant bit. What LSB means is that, it is the least amount of change in voltage that a data converter can detect. This slide shows you how this LSB is calculated. For example, it depends on two things, as I mentioned earlier: the reference voltage and resolution of the converter. That determines what LSB is for that system. If you look at the slide, LSB is a really small number. If you are using a 12-bit converter, and you are using a 2-volt reference input, which is a typical system. 12-bit is not super high in resolution. You are already getting under 1 millivolt as far as LSB that your system can tolerate. That is really small. If you are using, say, a sigma delta converter, very high resolution up to 20 bits, and 2-volt input range, you are getting somewhere around a couple of microvolts of LSB. I will cover that later, as far as using the DSP-to-Data Converter Compatibility Guide, and how you can use that in picking a data converter.

Resolution vs. Accuracy:
Good Accuracy Poor Resolution Poor Accuracy Poor Resolution Poor Accuracy Good Resolution Good Accuracy Good Resolution There is a distinct difference between resolution and accuracy. The targets above provide a sporting analogy. You have two dart contestants – a high quality one and a low quality one. The high quality person can throw his darts with a small “spread” – in other words, several darts will land within a small distance of each other, perhaps within a 1” circle. The low quality, or beginner dart thrower, will have a larger “spread” – for example, a 10” diameter area within which rounds that are thrown at a single target will land. Obviously, it’s easier to tell where a dart from the high quality thrower was supposed to land. Using the results of the high quality thrower, you can distinguish targets as close as an inch or two apart. The low quality thrower, with its larger “spread”, would generate a scatter of darts over the whole area being targeted. The high quality thrower has high resolution. It can be aimed at targets with only a small distance apart. The low quality thrower has low resolution, and can be used for throwing at the general area of a target, but if you need to distinguish between separate small targets it won’t do the job. 4 6-115

AC Specs SNR (Signal-to-Noise Ratio) –
RMS value representing the ratio of the amplitude of the desired signal to noise power below one half the sampling frequency. Measure of the strength of a signal to background noise. Contributes to the overall dynamic performance of the device at higher frequencies and affects the linearity at those frequencies. In the audio world, a low signal-to-noise ratio means the device has lots of hiss and static, while a high rating means clear-sounding audio. THD (Total Harmonic Distortion) – The ratio of the sum of the powers of all harmonic frequencies above the fundamental frequency to the power of the fundamental frequency. THD is usually expressed in dB. ENOB (Effective Number Of Bits) - The number of bits achieved in a real system. Is another way of specifying the SNR. ENOB = (SNR-1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this ENOB number of bits. SFDR (Spurious Free Dynamic Range) - The headroom available in an FFT plot. It is the distance in dB between the fundamental input and the worse spur. Fundamental Signal SFDR First Harmonic Second Harmonic Average Noise Floor

DC errors Offset Error – Gain Error – 111 Actual Transfer Function
Ideal Transfer Function Digital Output code 110 101 100 011 010 001 Actual Full Scale Range Analog Input Voltage 000 Ideal Full Scale Range Offset Error Offset Error – The offset error is the difference between the nominal and actual offset points. It is the difference in voltage between the first ideal code transition and the actual code transition of the ADC. This error affects all codes by the same amount and can usually be compensated for by a trimming process. If trimming is not possible, this error is referred to as the zero-scale error. Gain Error – The gain error is the difference between the ideal gain between zero and full scale on the transfer function and the actual gain after the offset error has been corrected to zero. This error represents a difference in the slope of the actual and ideal transfer functions and as such corresponds to the same percentage error in each step. This error can also usually be adjusted to zero by trimming.

DC Specs 111 Actual Transfer Function Ideal Transfer Function 110 Digital Output code < 1LSB DNL 101 100 011 010 > 1LSB DNL 001 000 Analog Input Voltage INL < 0 INL (Integral Nonlinearity Error) - (or simply linearity error) The deviation of the values on the actual transfer function from the ideal transfer function once the gain and offset errors have been nullified. The summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the INL at that step. The unit for INL is LSB. DNL (Differential Nonlinearity Error) – (or simply differential linearity) The differential nonlinearity error is the difference between an actual step width (for an ADC) or step height (for a DAC) and the ideal value of 1 LSB (Least Significant Bit). If the DNL exceeds 1 LSB, the magnitude of the output gets smaller for an increase in the magnitude of the input. In an ADC there is also a possibility that there can be missing codes (if DNL < -1LSB) i.e. one or more of the possible 2n binary codes are never output.

Major DNL Errors Input Voltage 111 110 101 100 011 010 001 000 1 2 3 4
1 2 3 4 5 6 7 Input Voltage ADC Missing Code

LOST??? Different Datasheets list specs in different terminologies
INL in LSB, mV, %, PPM Power in mW, V, I Gain error/drift in %FSR, μV

The Relevancy… Power (W) = Vin (V) X Ioper (A) LSB mV % PPM *
Cheat Book Power (W) = Vin (V) X Ioper (A) LSB mV % PPM * LSBX(2)[1].VrefX100 2N LSB X 100 LSB X 106 mV X 2N . (2)[1].Vref 100 mV . (2)[1] Vref mV X 104 (2)[1] .Vref % X 2N 100 % X (2)[1] .Vref % X 104 PPM X 2N 104 PPM X (2)[1] .Vref [1] The factor 2 in brackets is to be used for a bipolar device.

ADC Offset Errors Output Code Input Voltage 111 110 101 100 011 010
Ideal transfer characteristic 111 110 101 100 Output Code 011 Actual transfer characteristic 010 001 000 1 2 3 4 5 6 7 The figure above illustrates the transfer function on an ideal 3-bit converter. Offset error is defined as the difference between the nominal and actual offset points. For an ADC, the offset point is the midstep value when the digital output is zero. This error affects all codes by the same amount and can usually be compensated for by a trimming process. If trimming is not possible, this error is referred to as the zero-scale error. The ADS8344 is a 16-bit, 8-channel, 100-kHz converter ideal for use in battery-powered data acquisition systems. Offset error for the ADS8344 is ±1mV Now let’s look at the Gain error. Input Voltage 10

ADC Gain Errors Output Code Input Voltage 111 110 101 100 011 010 001
000 1 2 3 4 5 6 7 Gain error can be thought of as the deviation of the straight line through the transfer function at the intercept of full scale.Gain error is usually expressed as a percentage of Full-Scale Range (FSR), but can also be described in volts or LSBs. Gain error is dominated by errors in the converter’s reference voltage. Gain error for the ADS8344 is ±0.024% -1.2mV at +5V Now let’s discuss differential nonlinearity. Input Voltage 11

ADC INL Errors Output Code Input Voltage 111 110 101 100 011 010 001
Integral Linearity 111 110 101 100 Output Code 011 010 001 000 1 2 3 4 5 6 7 Integral linearity is used to describe the overall shape of the transfer function of the ADC. It is the deviation of code midpoints from their ideal location. The maximum deviation from the ideal transfer function is the worst-case integral linearity error. There are two ways to describe this. Either: Best fit End point The figure above shows the end-point linearity. For an ADC, the deviations are measured at the transitions from one step to the next. The ADS8344 has less than 6LSBs of INL Now, let’s examine some of the AC specifications that are important and how we derive them. Input Voltage 13

Differential Non Linearity
ADC DNL Errors Differential Non Linearity 111 110 101 100 Output Code 011 010 001 000 Differential nonlinearity is used to describe deviations from the ideal transition voltages in the converter’s transfer function. The figure above illustrates this. Each code transition should occur at an interval equal to 1LSB. If the code transitions occur at intervals of more than 1LSB, or less than 1LSB, errors in the ADC’s transfer function occur. Many 16-bit ADCs are specified to have no missing codes at some resolution below 16-bits. The ADS8344EB is guaranteed to have no missing codes to 15 bits. In this case, the output is only guaranteed to have 15 bits of information at any given output state. Finally, for the DC specification, let’s look at integral nonlinearity 1 2 3 4 5 6 7 Input Voltage 12

DNL Major Errors Output Voltage Output Code Input Code Input Voltage
ADC Missing Code DAC Non-monotonic 111 7 110 6 101 5 100 Output Code Output Voltage 4 011 3 010 2 001 1 000 1 2 3 4 5 6 7 Differential nonlinearity is used to describe deviations from the ideal transition voltages in the converter’s transfer function. The figure above illustrates this. Each code transition should occur at an interval equal to 1LSB. If the code transitions occur at intervals of more than 1LSB, or less than 1LSB, errors in the ADC’s transfer function occur. Many 16-bit ADCs are specified to have no missing codes at some resolution below 16-bits. The ADS8344EB is guaranteed to have no missing codes to 15 bits. In this case, the output is only guaranteed to have 15 bits of information at any given output state. Finally, for the DC specification, let’s look at integral nonlinearity 000 001 010 011 100 101 110 111 Input Code Input Voltage 12

Dynamic Specifications
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k Frequency - Hz Fundamental F H2 H3 H4 H5 H6 H7 H8 H9 Harmonics Amplitude (dB) 14-30

Spurious Free Dynamic Range (SFDR)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k Frequency / Hz Fundamental F SFDR Amplitude (dB) 14-32

Intermodulation Distortion, IMD
Amplitude (dB) 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k Frequency / Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 f2 - f1 2f1 - f2 f1 f2 2f2 - f1 f1 + f2 Intermodulation Distortion IMD Intermodulation distortion is a measurement of how much one frequency modulates another frequency within a system. Two frequencies are added together and applied to the system. The output harmonic products are measured and the value is also a measure of linearity. The more linear the system is, the lower the intermodulation products become. The second order terms are: f1 + f2 and f2 - f1. Third order terms are: 2f1 + f2, 2f1 - f2, f1 + 2f2 and f1 - 2f2. Especially when the distortion frequencies are close to the original frequencies, it will be very difficult to filter these out. Also in RF applications, the IMD products can mask out the information of very small- amplitude signals. 14-33

Measuring Noise RMS noise Peak-to-peak noise
Usually calculated from standard deviation of a series of samples Used to calculate ENOB Does not depend on noise type Peak-to-peak noise Gives “display resolution” Estimates typically assume that the noise is Gaussian In the demonstrations that follow, we will evaluate the noise performance of several classes of data acquisition circuitry. Although it is not the only figure of merit for a measurement system, noise performance, as we will see, has a great deal to do with its performance. Noise is the uncertainty of a measurement. In the days of 8 and 12-bit converter ICs, not as much attention was paid to this important aspect of electronic measurement, because it isn’t at all difficult to make an 8 or 12 bit converter noise-free. Ironically, it is low-noise delta-sigma converters that have brought this topic to the attention of many designers. Many engineers, used to getting steady values from their low-resolution converters, are dismayed when they find the output value of a 24-bit device fluctuating madly in its least significant bits. It’s not hard for an engineer, long used to working with low-resolution devices, to feel a bit cheated when he finds out that a 24-bit device isn’t really 24 bits when noise is taken into account! Unfortunately, the laws of physics make 24 bit noise-free resolution an extraordinarily difficult thing to obtain. Because of this, we need a way to measure and evaluate noise. In many AC measurement applications, such as audio and radio circuits, noise measurement techniques are well known, and typically done by analyzing the measured signal in the frequency domain. An FFT taken of a high-speed converter’s output provides a useful estimate of its noisiness. The figure measured here is called signal-to-noise ratio. In low-frequency measurement applications, however, the FFT isn’t nearly as useful, since we are measuring signals near DC. What is wanted instead is a measure of how certain we are of the value reported by the converter. We measure this by making many successive conversions with a single DC input applied to the converter and calculating statistical functions over the data. The two most common measurements of certainty for an ADC are RMS noise and peak-to-peak noise. RMS noise is the better figure-of-merit for an ADC, since it does not depend on the kind of noise. Peak-to-peak noise calculations are not as mathematically rigorous, and often assume that the noise is Gaussian in distribution, but they are essential for applications where the “flicker” or constancy of a displayed value must be known, such as weigh scales and thermometers.

Measuring Noise Calculating RMS noise Variance of a set of N samples:
Standard deviation: Effective number of bits (if samples are ADC codes): The equations in the slide are used to calculate RMS noise from a set of samples taken from the ADC being evaluated. The samples are assumed to be conversions made of the same DC input value. The first step is to calculate the mean, or average, value of the sample set. This is shown above as x with a bar above it. Next, the set’s variance is calculated. Variance is a measure of the average deviation of each sample from the average of all the samples. This is calculated by averaging the squares of the differences of each sample from the average. In the equation shown, N is the number of samples, and x-sub-i is the ith sample in the set. Standard deviation is variance expressed in a “standard” form, i.e., in the same units as the samples. This is simply the square root of the variance. (Note that standard deviation is a root- mean-square of the deviations from the average.) We can convert the standard deviation into several forms. The standard deviation itself is the RMS noise of the sample set in the same units as the sample set. If the samples are voltages, the standard deviation gives the RMS noise in volts, and if the samples are ADC codes, the standard deviation is the RMS noise in ADC codes (often called counts). A increasingly common measure is effective number of bits, or ENOB. This is the number of bit positions in each ADC code which are numerically unaffected by RMS noise. As shown above, it is the ADC’s word-length M minus the base 2 log of the standard deviation.

Measuring Noise Peak-to-peak noise

Signal to Noise Ratio (SNR)
VSIN VN N is number of bits of resolution Each extra bit provides approximately 6 dB improvement in the SNR ! Effective Number Of Bits (ENOB): SNR(dB) = 6.02 ´ N Quantization Noise +Q/2 -Q/2 Q ENOB = (SNR + D)(dB) 6.02 111 110 101 100 011 010 001 000 FS 0.5 FS Analog Input Voltage Digital Output Code Signal to Noise Ratio of Data Converter The Signal to Noise Ratio (SNR also often referred to as S/R) is a very important parameter for an A/D converter. The SNR is the ratio of the rms (root mean square) value of the input signal to the rms value of the quantization noise. The input signal is typically a sine wave with a maximum amplitude Vpeak. The rms value can be calculated as follows: The quantization noise voltage, which is also shown in the picture, is similar to a sawtooth voltage waveform. The rms value of a sawtooth waveform is: , where VP is Q/2. This results into . Therefore, the SNR can be derived. This can be written as: (1) The theoretical SNR of a 12-Bit ADC is approximately 74 dB. 14-29

Definition of "NOISE-FREE" code resolution
Effective resolution = log2 Full scale range RMS noise bits Noise-free Code resolution P-P noise P-Pnoise = × RMS noise (most commonly used ratio) = effective resolution – bits

Typical output RMS NOISE in uV and effective resolution in bits
Device (Semiconductor, Resistor) Noise Dominates at the Lower Frequencies (< 60 Hz notch) Quantization Noise Dominates at the Higher Frequencies

Aperture-Jitter (Sampling Uncertainty)
V VP -VP TA DtA Dv V+ Dv The Aperture Error is less than 1 LSB, if: In a 12-bit system with a maximum signal frequency of 20 MHz, the Aperture-Jitter has to be less than 3.8 ps !

Maximum Signal Frequency (MHz) * Equivalent converter SNR
Jitter Limits Maximum Signal Frequency (MHz) * Equivalent converter SNR SNR(dB) 130 120 110 100 90 80 70 60 50 40 30 *14 Bit *12 Bit *16 Bit 0.1 ps 0.3 ps 1 ps 3 ps 10 ps

Number of Input Channels
What is meant by 4 SE or 4 Diff? What is meant by 3x2 Diff? Multiplexer ADC Multiplexer ADC

Number of Input Channels
Single Ended (SE) vs Differential (Diff) SE: Referenced to ground Grounds may not be the same across causing a noisier environment Diff: Full-scale Range Wider code steps More accurate Ain Ain+ Ain-

ADC Interface Solutions Principle Configuration Choices
Single-Ended Input Differential Input + fs Vcm - fs + fs/2 Vcm -fs/2 Input ADC ADC IN IN + fs/2 Vcm -fs/2 IN IN Vcm Combined Differential inputs result in full-scale input of +fs to –fs Each input only requires 0.5x the swing compared to single-ended Both inputs require a Vcm for correct dc-bias Requires full input swing from +fs to –fs 2x the swing compared to differential Input signal at IN typically requires a common-mode voltage for bias Input IN\ also requires a Vcm for correct dc-bias Most CMOS pipeline ADCs are operated on a single-supply. This typically requires the inputs to be biased to a common-mode voltage, Vcm, which is typically set to mid-supply (+Vs/2). The converter inputs are often provided in differential form, but can be driven from the source in two ways: either single-ended or differential. Both configurations have their advantages and disadvantages.

Typical SPI Interface This is the simplest way to connect your ADC and host system together. In this case Chip Select is connected to the Slave Select pin of the processor. DCLK is connected to serial clock (SCLK) pin. Data out (Dout) pin is wired to Slave out Master In (SOMI) pin. Likewise, Data In is connected to Slave In Master Out (SIMO) pin. The Busy pin is shown tied to a general-purpose input here because not all processors have programmable edge-sensitive interrupt circuits. The MSP430F1149, 68HC11 microcontrollers and F2407 and C6000 family of DSPs posses these edge-triggered interrupt circuits. 43

I2C Interface — DSPs In electronic systems there are peripheral devices that must communicate with both each other and the outside world. To maximize hardware efficiency and simplify circuit design, Philips developed a simple bi-directional 2-wire, serial data (SDA) and serial clock (SCL) bus for Inter-Integrated Circuit control, simply called I2C. This I2C-bus supports any I2C fabrication process and, with the extremely broad range of I2C— compatible chips from Philips and other suppliers, it is the worldwide industry standard proprietary control bus. Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver), or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip must initiate a data transfer, or is only addressed. I2C is a multi-master bus, i.e. it can be controlled by more than one I2C connected to it. 48

Parallel—Digital Signal Processor
ADS8322 Processor ADS8322 CS GPO CS GPO CLK CLK CLK CLK R/W R/W RD decoder RD logic A[19:0] A[19:0] CONVST CONVST GPO GPO BUSY GPI D[15..0] D[15..0] D[15..0] D[15..0] BUSY logic INT Figure 1 Figure 2 Next let’s take a look at the general requirements for parallel converters. In this example, the device is memory mapped in data or I/O space. Some combinational logic is required to decode the address and select the device on the bus. In this case, there are approximately 21 wires from the converter and possibly up to 37 signals and some discrete logic involved from the processor side. The figure above shows a typical memory-mapped device. Some address decoding logic is needed to create the read signal for the converter. In some cases additional logic is required to transform a signal like the BUSY signal into an interrupt pulse that the processor can use. 46

AIN(+) ADC DAC AIN(-) +/- 200mV Maximum

DAC OUTPUT AIN(+) AIN(-)

Settling time of a DAC Analog Output (V) t Settling Time, ts Error
Band Final Value Analog Output (V) Glitch t Digital Change Delay Time

Monotonicity A DAC is monotonic if its output either increases or remains constant as the digital input increases, with the result that the output will always be a single-valued function of the input. The transfer function of a string DAC is guaranteed to be monotonic. What do we mean by monotonic? Monotonicity, by common definition, is having the property of never decreasing as the values of the independent variable or the subscripts of the terms increase. By electrical definition, a DAC is monotonic if its output either increases or remains constant as the digital input increases, with the result that the output will always be a single-valued function of the input.

Glitch Improvement Main Cause of Glitch
Charge in the switch causes node voltage to change temporarily More number of switches toggling when code changes – more glitch!! TSMC products uses Row-Column decoding (see next slide) – 30~40 switches toggling at any code change HPA07 products uses single decoder – maximum of two switches toggling at any time V IN + V a OUT Charge Q gets split - V R FB fb R t

Comparison of A/D and D/A key Specifications
Gain Error Error in slope of transfer curve. Same Offset Error Input which causes the first bit transition to occur (ideal is ½ lsb). Output which occurs for input code which should produce zero output. Linearity error Deviation of code midpoints from straight line. Deviation of analog output from straight line. Differential Nonlinearity Difference between actual width of code and ideal code (1 lsb). Difference between actual output increments and ideal (1 lsb) steps.