Presentation is loading. Please wait.

Presentation is loading. Please wait.

January 28th, 2011Clermont Ferrand, Paul Scherrer Institute Plans for the DRS5 Switched Capacitor Array Stefan Ritt.

Similar presentations


Presentation on theme: "January 28th, 2011Clermont Ferrand, Paul Scherrer Institute Plans for the DRS5 Switched Capacitor Array Stefan Ritt."— Presentation transcript:

1 January 28th, 2011Clermont Ferrand, Paul Scherrer Institute Plans for the DRS5 Switched Capacitor Array Stefan Ritt

2 January 28th, 2011Clermont Ferrand, Agenda DRS4 chip has been developed at PSI and has been shown at this Workshop in 2009/2010 No new chip developments since 2008, but – WaveDREAM board developed at PSI – CAEN VME board – ToF-PET Application under investigation New ideas for DRS5 to be designed in 2011 – Increased bandwidth – Zero dead time DRS4 Chip DRS4 Chip Evaluation Board

3 Stefan RittJanuary 28th, 2011Clermont Ferrand, DRS4 Chip

4 Stefan RittJanuary 28th, 2011Clermont Ferrand, DRS4 Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 8+1 ch. each 1024 bins, 4 ch. 2048, …, 1 ch Passive differential inputs/outputs Sampling speed 700 MHz … 5 GHz On-chip PLL stabilization Readout speed 30 MHz, multiplexed or in parallel

5 Stefan RittJanuary 28th, 2011Clermont Ferrand, Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) 850 MHz (-3dB) QFP package final bus width Measurement 800 MHz (-3dB) Evaluation board THS4508

6 Stefan Ritt ROI readout mode January 28th, 2011Clermont Ferrand, readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g MHz  3 us dead time  300,000 events / sec. e.g MHz  3 us dead time  300,000 events / sec.

7 Stefan Ritt Daisy-chaining of channels January 28th, 2011Clermont Ferrand, Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

8 Stefan Ritt Simultaneous Write/Read January 28th, 2011Clermont Ferrand, Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 FPGA Channel 0Channel 1 1 Channel 0 readout 8-fold analog multi-event buffer Channel 2 1 Channel 1 0 Expected crosstalk ~few mV

9 Stefan RittJanuary 28th, 2011Clermont Ferrand, DRS4 around the world Shipped (-Jan 2011): 2200 Chips 120 Evaluation Boards Shipped (-Jan 2011): 2200 Chips 120 Evaluation Boards

10 Stefan Ritt MEG PSI searches for  e  decay After ~10 years of chip design, DAQ setup, firmware programming, MEG runs with 3000 channels as designed 40 ps timing resolutions between all channels, running at 1.6 GS/s “Double buffer” readout mode increases life time to 99.7 % at 10 Hz event rate (3 MB/event) Took 400 TB in 2010 MEG Status January 28th, 2011Clermont Ferrand,

11 Stefan RittJanuary 28th, 2011Clermont Ferrand, Trigger and DAQ on same board SCA can only sample a limited (1024-bin window)  many application require a wider window, trigger capability would require continuous digitization Using a multiplexer in DRS4, input signals can simultaneously digitized at 120 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GSPS) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus

12 Stefan RittJanuary 28th, 2011Clermont Ferrand, “Slow” waveform and “Fast” window Continuous Waveform 120 MSPS (8 ns bins) Triggered DRS Waveform 1 GSPS (1 ns bins) up to 5 GSPS Triggered DRS Waveform 1 GSPS (1 ns bins) up to 5 GSPS Window only limited by RAM

13 Stefan RittJanuary 28th, 2011Clermont Ferrand, WaveDREAM Board Empty VME slot costs ~1kE USB is limited in speed (2.0) and scaling WaveDREAM board developed at PSI with GBit Ethernet New board planned VGA at input (10 mV – 10 V inputs) 16 Channels on Eurocard, MMCX connectors Standalone or cascadable Serial bus for data, trigger & synchronization Plug & Play Firmware: TDC, CFD, ADC, Scaler, MCA, … WaveDREAM (H. Friederich, PSI & ETH) WaveDREAM (H. Friederich, PSI & ETH) Pre- amp Pre- amp GBit Ethernet VGA DRS4 ADC FPGA RAM Eth Serial links and trigger New Board 16 chn + serial bus New Board 16 chn + serial bus

14 Stefan RittJanuary 28th, 2011Clermont Ferrand, Digital Oscilloscope Front-end

15 Stefan RittJanuary 28th, 2011Clermont Ferrand, Plug & Play Firmware Pre-designed modules for CFD, TDC, peak sensing ADC, … Modules can be configured by user and downloaded over Ethernet Chip Readout FIFO CFD TDC SCALER FIFO ADC FIFO Interface FIFO Data bus Parameter bus

16 Stefan RittJanuary 28th, 2011Clermont Ferrand, CAEN V1742 Board 32+2 Channels 12 bit 5 GS/s Digitizer VME64X + optical link New board design by CAEN in line with their ADC boards Firmware support by CAEN “Early adopter phase” started 2010, official board announcement March 2011 Desktop version planned

17 Stefan RittJanuary 28th, 2011Clermont Ferrand, Digital Pulse Processing (DPP) C. Tintori (CAEN) V. Jordanov et al., NIM A353, 261 (1994)

18 Stefan RittJanuary 28th, 2011Clermont Ferrand,  -n Pulse-shape Discrimination C. Tintori (CAEN)

19 Stefan Ritt DPP PSI January 28th, 2011Clermont Ferrand,

20 Stefan RittJanuary 28th, 2011Clermont Ferrand, Time-of-Flight PET Conventional electronics: CFD – TDC: 500 ps RMS TOF needs: ps >1 MHz rate Conventional electronics: CFD – TDC: 500 ps RMS TOF needs: ps >1 MHz rate C. Levin, Stanford University

21 Stefan Ritt Started fall 2010 after NSS/MIC in Knoxville (Siemens PET R&D home) New project started to replace current PET electronics with DRS4 (5) PCB ready summer 2011, firmware by Univ. Tübingen Simulations show that SCA technique can achieve 100 ps easily ToF-PET Project January 28th, 2011Clermont Ferrand, Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 1 FPGA Channel 0 Channel 1 ROI 20 samples (10 2 GS/s) * 30 ns / sample = 600 ns + 40 ns overhead = 640 ns  1 MHz rate 20 samples (10 2 GS/s) * 30 ns / sample = 600 ns + 40 ns overhead = 640 ns  1 MHz rate “Ping-Pong Scheme”

22 Stefan RittJanuary 28th, 2011Clermont Ferrand, DRS5 Chip

23 Stefan RittJanuary 28th, 2011Clermont Ferrand, Plans for DRS5 Increase analog bandwidth ~5 GHz Smaller input capacitance Increase sampling speed ~10 GS/s Switch to 180 nm technology Deeper sampling depth 8 x 4096 / chip Minimize readout time (“dead time free”) for muSR & ToF-PET (minor) reduction in analog readout speed (30 ns  20 ns) Implement FIFO technology J. Milnes, J. Howoth, Photek ~MHz event rate CTA  SR

24 Stefan Ritt 250 nm process dies out: 1 MPW run / year (UMC) Pro smaller feature size: Faster sampling speed Faster readout (?) More sampling cells / area (but: routing/capacitor limitation!) Con: Smaller VDD makes analog design difficult, with 1.2V it is almost impossible to obtain a 1V linear range Price: 130 nm 3 x more expensive Why 180nm ? January 28th, 2011Clermont Ferrand, Compromise: 180 nm

25 Stefan RittJanuary 28th, 2011Clermont Ferrand, Next Generation SCA Low parasitic input capacitance  High bandwidth Large area  low resistance bus, low resistance analog switches  high bandwidth Short sampling depth Digitize long waveforms Accommodate long trigger delay Faster sampling speed for a given trigger latency Deep sampling depth How to combine best of both worlds? How to combine best of both worlds?

26 Stefan RittJanuary 28th, 2011Clermont Ferrand, Cascaded Switched Capacitor Arrays shift register input fast sampling stage secondary sampling stage fast sampling cells (10 GSPS/180nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage 32 fast sampling cells (10 GSPS/180nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage

27 Stefan RittJanuary 28th, 2011Clermont Ferrand, Typical Waveform Only short segments of waveform need high speed readout

28 Stefan RittJanuary 28th, 2011Clermont Ferrand, Dead-time free acquisition Self-trigger writing of short 32-bin segments Simultaneous reading of segments Quasi dead time-free Data driven readout Ext. ADC runs continuously ASIC tells FPGA when there is new data Coarse timing from 300 MHz counter Fine timing by waveform digitizing and analysis in FPGA 20 * 20 ns = 0.4  s readout time  2 MHz sustained event rate Attractive replacement for CFD+TDC

29 Stefan RittJanuary 28th, 2011Clermont Ferrand, Conclusions DRS4 chip successfully used in many areas, true potential of SCA technology is just now discovered Planned DRS5 chip will increase BW and decrease readout dead time SCA technology should be able to replace most traditional electronics in particle detection


Download ppt "January 28th, 2011Clermont Ferrand, Paul Scherrer Institute Plans for the DRS5 Switched Capacitor Array Stefan Ritt."

Similar presentations


Ads by Google