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Application of the DRS Chip for Fast Waveform Digitizing Stefan Ritt Paul Scherrer Institute, Switzerland.

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Presentation on theme: "Application of the DRS Chip for Fast Waveform Digitizing Stefan Ritt Paul Scherrer Institute, Switzerland."— Presentation transcript:

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2 Application of the DRS Chip for Fast Waveform Digitizing Stefan Ritt Paul Scherrer Institute, Switzerland

3 March 14th, 2009TIPP09 Tsukuba2 Question ? 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ USB Power 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ USB Power

4 March 14th, 2009TIPP09 Tsukuba3 Switched Capacitor Array Shift Register Clock IN Out “Time stretcher” GHz  MHz Waveform stored Inverter “Domino” ring chain ns FADC 33 MHz

5 March 14th, 2009TIPP09 Tsukuba4 Switched Capacitor Array Cons No continuous acquisition Limited sampling depth Nonlinear timing Pros High speed (6 GHz) high resolution (11.5 bit resol.) High channel density (9 channels on 5x5 mm 2 ) Low power (10-40 mW / channel) Low cost (~ 10$ / channel) tt tt tt tt tt Goal: Minimize Limitations

6 March 14th, 2009TIPP09 Tsukuba5 DRS4 Designed for the MEG experiment at PSI, Switzerland UMC 0.25  m 1P5M MMC process (UMC), 5 x 5 mm 2, radiation hard 8+1 ch. each 1024 cells Differential inputs, differential outputs Sampling speed 500 MHz … 6 GHz, PLL stabilized Readout speed 30 MHz, multiplexed or in parallel

7 March 14th, 2009TIPP09 Tsukuba6 How to minimize dead time ? Fast analog readout: 30 ns / sample Parallel readout Region-of-interest readout Simultaneous write / read AD bit 8 channels

8 March 14th, 2009TIPP09 Tsukuba7 ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g MHz  3 us dead time  300,000 events / sec. e.g MHz  3 us dead time  300,000 events / sec.

9 March 14th, 2009TIPP09 Tsukuba8 Daisy-chaining of channels Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

10 March 14th, 2009TIPP09 Tsukuba9 Simultaneous Write/Read Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 FPGA Channel 0Channel 1 1 Channel 0 readout 8-fold analog multi-event buffer Channel 2 1 Channel 1 0 Expected crosstalk ~few mV

11 March 14th, 2009TIPP09 Tsukuba10 Trigger an DAQ on same board Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (6 GHz samples) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus “Free” local trigger capability without additional hardware

12 DRS4 Performance Test Results

13 March 14th, 2009TIPP09 Tsukuba12 Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) 850 MHz (-3dB) QFP package final bus width Simulation Measurement

14 March 14th, 2009TIPP09 Tsukuba13 Timing jitter t1t1 t2t2 t3t3 t4t4 t5t5 Inverter chain has transistor variations   t i between samples differ  “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i =  t i –  t nominal “Integral temporal nonlinearity” TI i =  t i – i  t nominal “Random aperture jitter” = variation of  t i between measurements Inverter chain has transistor variations   t i between samples differ  “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i =  t i –  t nominal “Integral temporal nonlinearity” TI i =  t i – i  t nominal “Random aperture jitter” = variation of  t i between measurements TD 1 TI 5

15 March 14th, 2009TIPP09 Tsukuba14 Fixed jitter calibration Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis

16 March 14th, 2009TIPP09 Tsukuba15 Sine Curve Fit Method S. Lehner, B. Keil, PSI i j y ji : i-th sample of measurement j a j f j  j o j : sine wave parameters  i : phase error  fixed jitter “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine  i using all measurements where sample “i” is near zero crossing Make several iterations “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine  i using all measurements where sample “i” is near zero crossing Make several iterations

17 March 14th, 2009TIPP09 Tsukuba16 Fixed Pattern Jitter Results TD i typically ~50 ps 5 GHz TI i goes up to ~600 ps Jitter is mostly constant over time,  measured and corrected Residual random jitter 3-4 ps RMS

18 Applications of the DRS4 Chip What can we do with this technology?

19 March 14th, 2009TIPP09 Tsukuba18 Flash ADC Technique 60 MHz 12 bit Q-sensitive Preamplifier PMT/APD Wire Shaper Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is fast enough All operations (CFD, optimal filtering, integration) can be done digitally Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is fast enough All operations (CFD, optimal filtering, integration) can be done digitally FADC TDC 5 GHz 12 bit Transimpedance Preamplifier FADC PMT/APD Wire Digital Processing Amplitude Time Baseline Restoration

20 March 14th, 2009TIPP09 Tsukuba19 How to measure best timing? Simulation of MCP with realistic noise and different discriminators J.-F. Genat et al., arXiv: (2008)

21 March 14th, 2009TIPP09 Tsukuba20 On-line waveform display click template fit pedestal histo  848 PMTs “virtual oscilloscope”

22 March 14th, 2009TIPP09 Tsukuba21 Pulse shape discrimination   Leading edge Decay time AC-coupling Reflections Example:  /  source in liquid xenon detector (or:  /p in air shower)

23 March 14th, 2009TIPP09 Tsukuba22  -distribution     = 21 ns   = 34 ns Waveforms can be clearly distinguished   = 21 ns   = 34 ns Waveforms can be clearly distinguished

24 March 14th, 2009TIPP09 Tsukuba23 Template Fit Determine “standard” PMT pulse by averaging over many events  “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize  2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values  Experiment 500 MHz sampling Pile-up can be detected if two hits are separated in time by ~rise time of signal

25 March 14th, 2009TIPP09 Tsukuba24 Timing Big Systems I Global Clock ~20 MHz Reference Clock for DRS4 PLL 2.5 MHz Reference Clock for timing channel LMK03000 Clock Conditioner (National Semiconductor) Jitter: 400 fs

26 March 14th, 2009TIPP09 Tsukuba25 Timing Big Systems II Channel 0 Domino Wave Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 PLL LMK03000 Experiment wide global clock DRS4 Chip Global clock locks all Domino Waves to same frequency and phase Residual random jitter: 25 ps Even better timing can be obtained by clock sampling MEG Experiment: Single LVDS clock distributed over 9 VME crates

27 March 14th, 2009TIPP09 Tsukuba26 Experiments using DRS chip MAGIC-II 400 channels DRS2 MEG 3000 channels DRS2 upgraded to DRS4 soon MEG 3000 channels DRS2 upgraded to DRS4 soon BPM for 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned)  PET

28 March 14th, 2009TIPP09 Tsukuba27 Availability DRS4 can be obtained from PSI on a “non-profit” basis Delivery “as-is” Costs ~ USD/channel ( JPY) USB Evaluation board as reference design VME boards from industry in channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz 32-channel 65 MHz/12bit digitizer “boosted” by DRS4 chip to 5 GHz

29 March 14th, 2009TIPP09 Tsukuba28 Conclusions Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 4 ps timing resolution ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this technology

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31 March 14th, 2009TIPP09 Tsukuba30 Datasheet

32 March 14th, 2009TIPP09 Tsukuba31 Signal-to-noise ratio (DRS3!) “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) “Fixed pattern” offset error of 5 mV RMS can be reduced to 0.35 mV by offset correction in FPGA SNR: 1 V linear range / 0.35 mV = 69 dB (11.5 bits) Offset Correction

33 March 14th, 2009TIPP09 Tsukuba32 Interleaved sampling delays (167ps/8 = 21ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 6 GSPS * 8 = 48 GSPS Possible with DRS4 if delay is implemented on PCB

34 March 14th, 2009TIPP09 Tsukuba33 Latch Constant Fraction Discr. Latch 12 bit Clock  + + MULT Latch 00 & <0 Delayed signal Inverted signal Sum


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