Presentation is loading. Please wait.

Presentation is loading. Please wait.

Paul Scherrer Institute The PSI DRS4 Integrated Circuit Chip Stefan Ritt.

Similar presentations


Presentation on theme: "Paul Scherrer Institute The PSI DRS4 Integrated Circuit Chip Stefan Ritt."— Presentation transcript:

1

2 Paul Scherrer Institute The PSI DRS4 Integrated Circuit Chip Stefan Ritt

3 2 March 15th, 2011DPP Workshop PSI Agenda Introduction to Switched Capacitor Array Chips – Comparison with FADCs – Overview of chips on the market The DRS4 chip – Design principles – Special features – Some applications New ideas for DRS5 chip to be designed in 2011 – Increased bandwidth – Zero dead time

4 Stefan Ritt 3 March 15th, 2011DPP Workshop PSI Introduction to Switched Capacitor Array Chips

5 Stefan Ritt 4 March 15th, 2011DPP Workshop PSI Detectors in Particle Physics Particles interact with matter and produce light: Signal: ~ 100’s mV ns

6 Stefan Ritt 5 March 15th, 2011DPP Workshop PSI Flash ADC Technique 60 MHz 12 bit Q-sensitive Preamplifier PMT/APD Wire Shaper Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is “fast” enough All operations (CFD, optimal filtering, integration) can be done digitally Shaper is used to optimize signals for “slow” 60 MHz FADC Shaping stage can only remove information from the signal Shaping is unnecessary if FADC is “fast” enough All operations (CFD, optimal filtering, integration) can be done digitally FADC TDC “Fast” 12 bit Transimpedance Preamplifier FADC PMT/APD Wire Digital Processing Amplitude Time Baseline Restoration

7 Stefan Ritt 6 March 15th, 2011DPP Workshop PSI Nyquist-Shannon Theorem If a function x(t) contains no frequencies higher than F Hertz, it is completely determined by giving its ordinates at a series of points spaced 1/(2F) seconds apart. If a detector produces frequencies up to 500 MHz (0.6 ns rise time), all information from that detector is recorded if sampled at 1 GSPS with good enough signal-to-noise ratio

8 Stefan Ritt 7 March 15th, 2011DPP Workshop PSI How to measure best timing? Simulation of MCP with realistic noise and different discriminators K. Byrum, H. Frisch, J.-F. Genat et al., IEEE Trans.Nucl.Sci.57, 525 (2010)

9 Stefan Ritt 8 March 15th, 2011DPP Workshop PSI Currently available fast ADCs 8 bits – 3 GS/s – 1.9 W  24 Gbits/s 10 bits – 3 GS/s – 3.6 W  30 Gbits/s 12 bits – 3.6 GS/s – 3.9 W  43.2 Gbits/s 14 bits – 0.4 GS/s – 2.5 W  5.6 Gbits/s 1.8 GHz! 24x1.8 Gbits/s Requires high-end FPGA Complex board design FPGA power Requires high-end FPGA Complex board design FPGA power

10 Stefan Ritt 9 March 15th, 2011DPP Workshop PSI ADC boards PX1500-4: 2 Channel 3 GS/s 8 bits ADC12D1X00RB: 1 Channel 1.8 GS/s 12 bits 1-10 k€ / channel

11 Stefan Ritt 10 March 15th, 2011DPP Workshop PSI Switched Capacitor Array Shift Register Clock IN Out “Time stretcher” GHz  MHz Waveform stored Inverter “Domino” ring chain ns FADC 33 MHz

12 Stefan Ritt 11 March 15th, 2011DPP Workshop PSI Switched Capacitor Array Cons No continuous acquisition Limited sampling depth Nonlinear timing Pros High speed (5 GHz) high resolution (11.5 bit) High channel density (9 channels on 5x5 mm 2 ) Low power (10-40 mW / channel) Low cost (~ 10€ / channel) tt tt tt tt tt Goal: Minimize Limitations STRAW3 TARGET LABRADOR3 G. Varner Univ. of Hawaii AFTER MATACQ SAM D. Breton E. Delagnes CEA Saclay DRS1DRS2 DRS3DRS4 This talk

13 Stefan Ritt 12 March 15th, 2011DPP Workshop PSI The DRS4 Chip

14 Stefan Ritt 13 March 15th, 2011DPP Workshop PSI CMOS process (typically 0.35 … 0.13  m)  sampling speed Number of channels, sampling depth, differential input PLL for frequency stabilization Input buffer or passive input Analog output or (Wilkinson) ADC Internal trigger Exact design of sampling cell Design Options PLL ADC Trigger

15 Stefan Ritt 14 March 15th, 2011DPP Workshop PSI DRS History Temperature Dependence ~kT DRS2 I DRS3 0.2 pF 20 pF DRS1 Tiny signal DRS4 PLL-regulated Sampling Speed DSC Roger Schnyder, Christian Brönnimann,  Roberto Dinapoli

16 Stefan Ritt 15 March 15th, 2011DPP Workshop PSI DRS4 Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm2, radiation hard 8+1 ch. each 1024 bins, 4 ch. 2048, …, 1 ch Passive differential inputs/outputs Sampling speed 700 MHz … 5 GHz On-chip PLL stabilization Readout speed 30 MHz, multiplexed or in parallel

17 Stefan Ritt 16 March 15th, 2011DPP Workshop PSI 12 bit resolution 11.5 bits effective resolution <8 bits effective resolution

18 Stefan Ritt 17 March 15th, 2011DPP Workshop PSI Bandwidth Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) 850 MHz (-3dB) QFP package final bus width Simulation Measurement Ueli Hartmann ~2 nH Bond wireParasitic ~10 pF

19 Stefan Ritt 18 March 15th, 2011DPP Workshop PSI Bump Bonding Reduce input inductance by using bump bonding instead of wire bonding 200  m 75  m

20 Stefan Ritt 19 March 15th, 2011DPP Workshop PSI How to minimize dead time ? Fast analog readout: 30 ns / sample Parallel readout Region-of-interest readout Simultaneous write / read AD bit 8 channels

21 Stefan Ritt 20 March 15th, 2011DPP Workshop PSI ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g MHz  3 us dead time  300,000 events / sec. e.g MHz  3 us dead time  300,000 events / sec.

22 Stefan Ritt 21 March 15th, 2011DPP Workshop PSI Daisy-chaining of channels Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Domino Wave 1 clock enable input enable input DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells Chip daisy-chaining possible to reach virtually unlimited sampling depth

23 Stefan Ritt 22 March 15th, 2011DPP Workshop PSI Simultaneous Write/Read Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 0 FPGA Channel 0Channel 1 1 Channel 0 readout 8-fold analog multi-event buffer Channel 2 1 Channel 1 0 Expected crosstalk ~few mV

24 Stefan Ritt 23 March 15th, 2011DPP Workshop PSI DRS4 around the world Shipped (-Jan 2011): 2200 Chips 120 Evaluation Boards Shipped (-Jan 2011): 2200 Chips 120 Evaluation Boards

25 Stefan Ritt 24 March 15th, 2011DPP Workshop PSI MEG PSI searches for  e  decay After ~10 years of chip design, DAQ setup, firmware programming, MEG runs with 3000 channels as designed 40 ps timing resolutions between all channels, running at 1.6 GS/s “Double buffer” readout mode increases life time to 99.7 % at 10 Hz event rate (3 MB/event) Took 400 TB in 2010 MEG Experiment

26 Stefan Ritt 25 March 15th, 2011DPP Workshop PSI MEG 4 x DRS4 LMK channels 3000 Channels

27 Stefan Ritt 26 March 15th, 2011DPP Workshop PSI On-line waveform display click template fit pedestal histo  848 PMTs “virtual oscilloscope”

28 Stefan Ritt 27 March 15th, 2011DPP Workshop PSI Crosstalk elimination Crosstalk removal by subtracting empty channel Hit subtract

29 Stefan Ritt 28 March 15th, 2011DPP Workshop PSI Template Fit Determine “standard” PMT pulse by averaging over many events  “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize  2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values  Experiment 500 MHz sampling

30 Stefan Ritt 29 March 15th, 2011DPP Workshop PSI Trigger and DAQ on same board SCA can only sample a limited (1024-bin window)  many application require a wider window, trigger capability would require continuous digitization Using a multiplexer in DRS4, input signals can simultaneously digitized at 120 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GSPS) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus

31 Stefan Ritt 30 March 15th, 2011DPP Workshop PSI “Slow” waveform and “Fast” window Continuous Waveform 120 MSPS (8 ns bins) Triggered DRS Waveform 1 GSPS (1 ns bins) up to 5 GSPS Triggered DRS Waveform 1 GSPS (1 ns bins) up to 5 GSPS Window only limited by RAM

32 Stefan Ritt 31 March 15th, 2011DPP Workshop PSI Sine Curve Fit Method S. Lehner, B. Keil, PSI i j y ji : i-th sample of measurement j a j f j  j o j : sine wave parameters  i : phase error  fixed jitter “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine  i using all measurements where sample “i” is near zero crossing Make several iterations “Iterative global fit”: Determine rough sine wave parameters for each measurement by fit Determine  i using all measurements where sample “i” is near zero crossing Make several iterations

33 Stefan Ritt 32 March 15th, 2011DPP Workshop PSI Fixed Pattern Jitter Results TD i typically ~50 ps 5 GHz TI i goes up to ~600 ps Jitter is mostly constant over time,  measured and corrected Residual random jitter 3-4 ps RMS Achievable resolution exceeds best CFD + HPTDC

34 Stefan Ritt 33 March 15th, 2011DPP Workshop PSI Time-of-Flight PET Conventional electronics: CFD – TDC: 500 ps RMS TOF needs: ps >1 MHz rate Conventional electronics: CFD – TDC: 500 ps RMS TOF needs: ps >1 MHz rate C. Levin, Stanford University

35 Stefan Ritt 34 March 15th, 2011DPP Workshop PSI Started fall 2010 after NSS/MIC in Knoxville (Siemens PET R&D home) New project started to replace current PET electronics with DRS4 (5) PCB ready summer 2011, firmware by Univ. Tübingen Simulations show that SCA technique can achieve 100 ps easily ToF-PET Project Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 1 FPGA Channel 0 Channel 1 ROI 20 samples (10 2 GS/s) * 30 ns / sample = 600 ns + 40 ns overhead = 640 ns  1 MHz rate 20 samples (10 2 GS/s) * 30 ns / sample = 600 ns + 40 ns overhead = 640 ns  1 MHz rate “Ping-Pong Scheme”

36 Stefan Ritt 35 March 15th, 2011DPP Workshop PSI DRS5 Chip Ideas

37 Stefan Ritt 36 March 15th, 2011DPP Workshop PSI Plans for DRS5 Increase analog bandwidth ~5 GHz Smaller input capacitance Increase sampling speed ~10 GS/s Switch to 110 nm technology Deeper sampling depth 8 x 4096 / chip Minimize readout time (“dead time free”) for muSR & ToF-PET (minor) reduction in analog readout speed (30 ns  20 ns) Implement FIFO technology J. Milnes, J. Howoth, Photek ~MHz event rate CTA  SR

38 Stefan Ritt 37 March 15th, 2011DPP Workshop PSI Next Generation SCA Low parasitic input capacitance  High bandwidth Large area  low resistance bus, low resistance analog switches  high bandwidth Short sampling depth Digitize long waveforms Accommodate long trigger delay Faster sampling speed for a given trigger latency Deep sampling depth How to combine best of both worlds? How to combine best of both worlds?

39 Stefan Ritt 38 March 15th, 2011DPP Workshop PSI Cascaded Switched Capacitor Arrays shift register input fast sampling stage secondary sampling stage fast sampling cells (10 GSPS/110nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage 32 fast sampling cells (10 GSPS/110nm CMOS) 100 ps sample time, 3.1 ns hold time Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz) Shift register gets clocked by inverter chain from fast sampling stage

40 Stefan Ritt 39 March 15th, 2011DPP Workshop PSI How noise affects timing voltage noise band of signal timing jitter arising from voltage noise timing jitter is much smaller for faster rise-time voltage noise  u timing uncertainty  t signal height U rise time t r number of samples on slope

41 Stefan Ritt 40 March 15th, 2011DPP Workshop PSI TDC vs. Waveform Digitizing Q-sensitive Preamplifier PMT/APD Wire Shaper TDC Constant Fraction Discriminator CFD and TDC on same board  crosstalk CFD depends on noise on single point, while waveform digitizing can average over several points Inverter chain is same both in TDCs and SCAs Can we replace TDCs by SCAs?  yes if the readout rate is sufficient CFD and TDC on same board  crosstalk CFD depends on noise on single point, while waveform digitizing can average over several points Inverter chain is same both in TDCs and SCAs Can we replace TDCs by SCAs?  yes if the readout rate is sufficient

42 Stefan Ritt 41 March 15th, 2011DPP Workshop PSI Typical Waveform Only short segments of waveform need high speed readout

43 Stefan Ritt 42 March 15th, 2011DPP Workshop PSI Dead-time free acquisition Self-trigger writing of short 32-bin segments Simultaneous reading of segments Quasi dead time-free Data driven readout Ext. ADC runs continuously ASIC tells FPGA when there is new data Coarse timing from 300 MHz counter Fine timing by waveform digitizing and analysis in FPGA 20 * 20 ns = 0.4  s readout time  2 MHz sustained event rate Attractive replacement for CFD+TDC DRS5

44 Stefan Ritt 43 March 15th, 2011DPP Workshop PSI Plug & Play Firmware Emphasis shift from dedicated hardware to firmware Pre-designed modules for CFD, TDC, peak sensing ADC, … Modules can be configured by user and downloaded ADC Readout FIFO CFD TDC SCALER FIFO ADC FIFO Interface FIFO Data bus Parameter bus

45 Stefan Ritt 44 March 15th, 2011DPP Workshop PSI Conclusions DRS4 chip successfully used in many areas, true potential of SCA technology is just now discovered Planned DRS5 chip will increase BW and decrease readout dead time SCA technology should be able to replace most traditional electronics in particle detection

46 Stefan Ritt 45 March 15th, 2011DPP Workshop PSI Thanks to … Roland Horisberger: Original Idea Roberto Dinapoli: Analog Design of DRS3+4 Ueli Hartmann: DRS4 Evaluation Boards PSI chip design core team


Download ppt "Paul Scherrer Institute The PSI DRS4 Integrated Circuit Chip Stefan Ritt."

Similar presentations


Ads by Google