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Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics.

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Presentation on theme: "Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics."— Presentation transcript:

1 Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics Research Center Georgia Institute of Technology SLIP Workshop April 2000 Supported by DARPA and SRC

2 4/9/002 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

3 4/9/003 Motivation 10% of Interconnects = 80% of Wire Length. KEEP INTERCONNECTS SHORT!!

4 4/9/004 Motivation Each gate has more neighboring gates. 2D 3D

5 4/9/005 Motivation Reduction of gate pitch due to smaller wire-limited area. 2D 3D

6 4/9/006 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

7 4/9/007 3D Architecture Concepts Stratum - A layer of transistors with its tiers of interconnects. Tier - A pair of orthogonal metal levels with equal pitch. Stratum 1 Stratum 2 Tier 2 Tier 1 Tier 2 Tier 1

8 4/9/008 3D Architecture Concepts Stratal- to gate- pitch ratio r. Stratum 1 Stratum 2

9 4/9/009 3D Architecture Concepts Importance of r Height of metal stack is at least as great as the gate pitch (r > 1). Substrate thickness for mechanical stability. Thermal/electrical insulation of strata. r affects the probability of running an interconnect vertically.

10 4/9/0010 3D Architecture Concepts Gate pair – two gates separated by a given manhattan length. Length in manhattan geometry.

11 4/9/0011 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

12 4/9/0012 Derivation of 3D Model Need two values. –Number of expected interconnects between a gate pair (probability of occupation). Use Rents Rule. –Number of gate pairs (density of states). Use discrete convolution.

13 4/9/0013 Derivation of 3D Model Number of Expected Interconnects Expression from Rents Rule. ABC B B B B B C C C C C ABBC 2D 1D

14 4/9/0014 Derivation of 3D Model Manhattan sphere instead of circles

15 4/9/0015 Derivation of 3D Model Edge effects. Horizontal

16 4/9/0016 Derivation of 3D Model Edge effects. Vertical

17 4/9/0017 Derivation of 3D Model Use of averaging to avoid both horizontal and vertical edge effects. A function for the number of starting gates must be defined. Number of Gate Pairs Number of Starting Gates

18 4/9/0018 Derivation of 3D Model Starting gate – a gate that can serve as the N A of a gate pair for a given length. X X X XX X X X X 1D 2D X X X X X Length = 5 X

19 4/9/0019 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

20 4/9/0020 Comparison with 2D

21 4/9/0021 Variable r

22 4/9/0022 Variable Strata

23 4/9/0023 Wire Demand

24 4/9/0024 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

25 4/9/0025 Optimization L n-1 Interconnect Distribution Area Required Delay Equation Solve equations simultaneously. p n is pitch required such that wire length L n meets delay. L n is limited by the available area for a tier and the pitch. LnLn DnDn

26 4/9/0026 Optimization Metal Levels Wire-Limited Area 50% reduction in metal levels 39% reduction in area 92% reduction in area 950 MHz

27 4/9/0027 Optimization 14x increase in clock frequency 63% reduction in area Wire-Limited Clock Frequency

28 4/9/0028 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

29 4/9/0029 Limitations Pad - Stratum 1 Pad - Stratum 2 Alignment Tolerance Cross-section Vertical Wiring Density Vertical interconnect pitch must be greater than alignment tolerance. Demonstrated alignment tolerance : 3 microns.

30 4/9/0030 Limitations Restrictions placed by density of vertical interconnects may require increased area. For frequency optimization, required alignment tolerance is 0.34 microns. Via aspect ratio may also add limitations on vertical wiring density.

31 4/9/0031 Outline Motivation 3D Architecture Concepts Derivation of 3D Model Results of Model Optimization of Interconnects Wiring Density Limitations Conclusions

32 4/9/0032 Conclusions A new model has been derived for interconnect distributions in 2D and 3D architectures. 14x increase in wire-limited clock frequency, 92% reduction in wire-limited area, or 50 % reduction in metal levels for 3D system. Restrictions on vertical interconnect density may compromise the advantages of 3D architectures.


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