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Switching & Logic Laboratory

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Presentation on theme: "Switching & Logic Laboratory"— Presentation transcript:

1 Switching & Logic Laboratory
Truth Tables & PLACE Switching & Logic Laboratory

2 Overview Interface Truth Tables JED file

3 Pre Laboratory 1 Get out K-maps and equation
Show K-maps and equations to laboratory assistant. If process not complete, leave laboratory at end of slides and complete at table in hall for 10 point penalty Else continue with task 1.

4 PEEL Interface System + 5 V D0 D1 D2 D3 DP SegG SegF SegE SegD SegC
7-Segment Display On Daughter Board + 5 V D0 D1 D2 D3 DP SegG SegF SegE SegD SegC SegB SegA V0 V1 V2 V3 Vector 1.0 PEEL On Daughter Board Clock “0” “1” myPEEL

5 Option 1 0 = on and 1 = off Input Output 0000 11111100 0001 01100000
. . . 1 = on and 0 = off

6 Option 2 0 = on and 1 = off Input Output 0000 00000011 0001 10011111
. . . 0 = on and 1 = off

7 Enter Truth Table Data TRUTH_TABLE FUNCTIONS
( I1 I0 -> O3 O2 O1 O0) > > > > END;

8 Seven Segment Display Codes
B C F E

9 Demonstrate WinPLACE and
Truth Tables here.

10 Sequence Select 18CV8 device Title, Name, Date, and Description
Label pins Allocate truth table header Enter table data Compiler truth table Simulate, check results, append vectors Program PEEL and verify design by exercising

11 Task 2 RED file contains reduced eaquation version of PSF file
Equations SEGA.COM = !D0 & !D2 # D0 & !D1 & D3 # !D1 & !D2 & D3 # D1 & !D3 # D0 & D2 & !D3;

12 PEEL Column & Row Layout
Column 0 to Column 35 Row 0 to Row7 Column 12, Row 4 PEELs used column and row notation for each fuse. Note fuse at each intersection.

13 Linear Array Layout of JED File
L0035 L0000 1 2 3 4 5 6 7 L0036 = 1*36+0 L0071 = 1*36+35 L0287 = 7*36+35 = 287

14 Col-Row to/from Linear Array
Column & Row to Linear Array L = Row*36 + Column L = 17* = L0633 Linear Array to Coumn & Row Row = L/36 Column = L%36 Row = 633/36 = = 17 Colum = 633%36 = *36 = 21

15 Pin 17 Linear Address Range
19 18 17 16 5 4 1 3 2 20 21 22 23 CLK D0 D1 D2 D3 SEGF 16*36+0 = L0576 23*36+35 = L0863

16 File format - Task 3 Comment Pins Fuses Default Note Location & Logic

17 File format - Task 3 1 = Blown 0 = Not Blown Pn Pn’ Result 1 1 1
N Output Pin 19* p1 p11 p2 p19 p3 p18 p4 p17 p5 p16 p6 p15 p7 p14 p8 p13 p9p12 Pn Pn’ Result Pn’ Pn = PnPn’ 1 = Blown 0 = Not Blown p19 = !p2•p3•p4•p5 or DP = !D0•D1•D2•D3

18 Big Picture -- Task 4 Task 1 Task 4 0 0 0 0 1 1 1 1 1 1 0 0
SEGF = !D0 & !D1 & D2 & D3 # D0 & D1 & !D2 & D3 # !D0 & D1 & !D2 & D3 # D0 & !D1 & !D2 & D3 # !D0 & !D1 & !D2 & D3 # !D0 & D1 & D2 & !D3 # D0 & !D1 & D2 & !D3 # !D0 & !D1 & D2 & !D3 # !D0 & !D1 & !D2 & !D3; SEGG = D0 & !D1 & D2 & D3 # D0 & D1 & !D2 & D3 # !D0 & D1 & !D2 & D3 # D0 & !D1 & D2 & !D3 # !D0 & !D1 & D2 & !D3 # D0 & D1 & !D2 & !D3 # !D0 & D1 & !D2 & !D3; DP = !D0 & D1 & D2 & D3; SEGA= !D0 & !D1 & D2 & D3 # !D0 & D1 & !D2 & D3 # D0 & !D1 & !D2 & D3 # !D0 & !D1 & !D2 & D3 # D0 & D1 & D2 & !D3 # !D0 & D1 & D2 & !D3 # D0 & !D1 & D2 & !D3 # D0 & D1 & !D2 & !D3 # !D0 & D1 & !D2 & !D3 # !D0 & !D1 & !D2 & !D3; Task 4

19 Big Picture Continued .PSF Task 1 .RED .JED .PSF Task 4 BP-1400
TRUTH_TABLE SEVSEG D3 D2 D1 D0 SEGA SEGB SEGC SEGD SEGE SEGF DP • • • • • SEGA = !D0&D1&D2&D3# • • • • • L …11* .PSF Task 4 SEGA = !D0*D1*D2*D3+ • • • • • BP-1400


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