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Study of excess heat capacity and suppressed Kapitza conductance in TES devices Y. Zhao, Cornell University, J. Appel, Princeton University, J. A. Chervenak, NASA GSFC, R. Doriese, NIST Boulder, S. Staggs, Princeton University

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Anomalous behavior in leg isolated bolometers Lueker – reports decoupling of TES from dielectric membrane in SiN spiderweb (IEEE Trans Appl. Supercon. 19 p 496 (2009)) Excess heat capacity measurements in SiN / TES Kenyon, et. al., IEEE Trans Appl. Supercon. 19 p. 524 (2009) D. J. Goldie et. al. J. Appl. Phys. 105, 074512 (2009) Eckart, et. al., LTD-13, AIP conf. proc. 1185, 430 (2009) We are studying the magnitude of these effects in a series of Si devices / possible relationship

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Engineering decoupling into bolometers Single crystal silicon for membrane Devices side by side on same chip; with and without trench isolation near TES Measure IV characteristic and impedance curves to extract all parameters in same environment (takes out common mode effects of fridge setup, readout electronics, magnetic field) TES 1.055 mm 2 Si 20 micron leg Local thermal Isolation for TES

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Detector Fabrication SOI wafer (1.4 micron single crystal device layer) Backetch to membrane, remove buried oxide in HF, release part in SF6 RIE Bias power for 32 pixels on single chip Prior to frontetchPost frontetch Pixel Params (1.055 mm 2 Si) Expected values C(TES)~0.1 pJ/K [normal] C(Si)~0.1 pJ/K [Debye] G TS ~7e5 pW/K [Kapitza calc] G TS ~5e4 pW/K [empirical scaling] No decoupling below 100 kHz anticipated

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Series of Four Test Devices PartPixel NumBias power (pW)Tc (mK) A (20 m, no addtl stencil) 539.7551.7 B (20 m, 1 stencil) 1138.2550.7 C (20 m, 2 stencil) 932.7550.1 D (5 m, 1 stencil) 109.4551.3 Detector parameters from IV analysis AB C D

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Models for Detector Impedance Model (a) – Ideal TES – Concentric Semicircles for Impedance Curves Model (b) locates the excess heat capacity in parallel with the TES, whereas Model (c) looks at a series heat capacity, such as one associated with the narrow legs

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Model enables decoupling of components in electrothermal circuit Fits for heat capacities (3), thermal conductances (3),,, (but not temperatures) Allows for second heat capacity to be coupled (intended to be electrons in absorber film, though absorber is NOT on these devices) Compare to measured impedance (swept sine method; Lindemann method for normalizing amplifier chain transfer function) Extracts variations in G ts that were designed

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Typical Impedance and quality of fit Three block fit better than two block, indicating presence of third time constant

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Results from model Model attempts to extract absolute numbers – but, for example, C s + C a is quite collosal (>10x) compared to Debye value for the volume of Si. G ts of device 10x low compared to empirical value for metal to dielectric at these temps (100x lower than Kapitza calculation Au to Si).

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20 micron leg / 1 mm 2 Si Pixel type A – No added perforation Models b and c both fit the top components (C_Si, G_TS, etc.) with same parameters Excess heat cap is higher for model c – series model Param10% Rn50% Rn90% RnCalculated C s (pJ/K)0.850.890.910.13 G ts (pW/K)586661336234>5e4 C a (pJ/K)0.620.650.66 G sa (pW/K)116912231244 C l (pJ/K)0.860.900.92

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To compare parameter values among various devices Bootstrapping method (random sampling of input data set) gives 5% error bars on 68% confidence interval on fit parameters Rules out covariance, overfitting issues with method Establishing Confidence Intervals on extracted parameters

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Tabulated Data from Three Block Models ParamABCD Comment C t (pJ/K)0.25 0.240.22 Similar / higher than expectation G ts (pW/K)6130281012002250 Engineered by perforations C s (pJ/K)0.891.021.030.96 15% increase in both models G a (pW/K)1220900700470 Hanging model G sl (pW/K)15601230990550 Series model C a (pJ/K)0.650.680.760.56 Hanging model C l (pJ/K)0.901.011.200.68 Series model Models fit to same impedance curves for T base =320 mK; 50% Rn

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Excess heat capacity versus thermal decoupling in devices with same leg width (Dev A, B, C) Decoupling expected from introduction of stencils near TES Unexpected rise in heat capacity (greater than confidence interval of model)

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Compare Devices B and D: different leg width Changing leg width causes changes in all internal parameters in supposedly identical structures

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Data summary C s and sum of excess C correlated with G ts for devices where legs are same width; 15% C increase engineered with small slots in otherwise identical devices Trend with narrower leg isolation is that total excess heat capacity is lower but its thermalization slower

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Are model results consistent with contamination? Observable contamination evident on surfaces of devices/ especially edges. (Teflon formed during silicon dry etch) Heat cap changes without change in volume /surface area Perim increases from A -> B->C (heat cap went up) Perim increases from A ->D (heat cap dropped)

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Speculation about G ts - C s correlation Phonons emitted by metal on dielectric can elastically scatter in the membrane until reabsorbed in the metal, suppressing measured G TS from Kapitza value Since TES is constantly dissipative, persistence of population of excess phonons in silicon membrane region contribute to the statistical ensemble determining the heat capacity

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Wheres the second heat capacity? (further speculation) Effect of leg width on G ts may further imply long lived phonons; phonon modes that are elastically reflected into and out of leg (thus more weakly coupled) That a large heat capacity is directly associated with TES NOT indicated by model (C t is near constant in all models; G ts consistent with expectation)

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Conclusion 4 devices measured that show excess heat cap and thermal decoupling of metal from dielectric Models further indicate G ts varies as expected; other internal parameters interact / vary unexpectedly While small volume of teflon on device edges is visible, it does not match the model consistently in all four cases Correlation of G ts with C s & C a suggests mechanism for intrinsic non-idealities of leg isolated TES

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