Download presentation

Presentation is loading. Please wait.

Published byLia Merwin Modified over 3 years ago

1
**Technology CAD: Technology Modeling, Device Design and Simulation S**

Technology CAD: Technology Modeling, Device Design and Simulation S. Saha and B. Gadepally 2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India S. Saha and B. Gadepally

2
**Technology CAD: Technology Modeling, Device Design and Simulation**

Coordinator: Prof. Bhaskar Gadepally Adjunct Prof., Electrical Engineering, IIT Bombay Chairman, Reliance Software Consulting, Inc. 155 E. Campbell Ave., Campbell, CA (USA) 2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India S. Saha and B. Gadepally

3
**Technology CAD: Technology Modeling, Device Design and Simulation**

Instructor: Dr. Samar Saha Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, CA (USA) 2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India S. Saha and B. Gadepally

4
**Tutorial Outline Prof. B. Gadepally: Dr. S. Saha:**

Introduction and Tutorial Overview. Dr. S. Saha: Front-end Process Technology CAD (TCAD) Models and Process Simulations Device TCAD Models and Device Simulations Industrial Application of TCAD Calibration of Process and Device Models Industrial Application of TCAD in Device Research Compact / SPICE Modeling. S. Saha and B. Gadepally

5
**Technology CAD: Technology Modeling, Device Design and Simulation Introduction and Tutorial Overview**

2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India Bhaskar Gadepally

6
**Overview of IC Technology**

In the past three decades: device densities have grown exponentially device and technology complexities have increased significantly design constraints are many-fold: ultra thin oxide interconnect power supply technology development cost has increased enormously. Bhaskar Gadepally

7
**Overview of IC Technology**

Channel Engineering - non-uniform channel doping - Quantum Mechanical effects - low-diffusivity impurities - threshold voltage control Source-Drain Engineering - ultra-shallow extensions - low-energy implants - RTA/LTA techniques - halo optimization p-substrate p-well n-well n+ PMOS p+ STI Halo P+ poly Spacer NMOS (Shallow Trench Isolation) Gate Engineering: Dielectric - ultra-thin gate oxide - direct tunneling - high-k dielectrics Gate Engineering: Stack - dual-poly / poly depletion - work function engineering - interface properties N+ poly Bhaskar Gadepally

8
Overview of IC Devices New device and device physics are continuously evolving: nano-scale devices microscopic diffusion quantum mechanical carrier transport molecular dynamics quantum chemistry high-frequency interconnect behavior. Bhaskar Gadepally

9
Technology CAD With the increased complexities in IC process and device physics: intuitive analysis is no longer possible to design advanced IC processes and devices TCAD tools are crucial for efficient technology and device design to quantify potential roadblocks to indicate new solutions for continuos scaling of devices. Bhaskar Gadepally

10
**Technology CAD Scope of TCAD:**

front-end process modeling and simulation implant, diffusion, oxidation etc. numerical device modeling and simulation I - V, C - V etc. simulation topography modeling and simulation deposition, lithography, etching etc. device modeling for circuit simulation compact / SPICE modeling interconnect simulation capacitance, inductance etc. Bhaskar Gadepally

11
Tutorial Objective Offer insight into the physical basis of TCAD, especially, bulk-process and device TCAD. Describe systematic methodologies for an effective application of TCAD tools. Describe systematic calibration methodology for predictive usage of TCAD tools: process models device models. Offer users sufficient insight to leverage new tools. Bhaskar Gadepally

12
**Session 1: Bulk-Process Simulation**

Front-end process models implemented in process TCAD tools: ion implantation models analytical Monte Carlo microscopic diffusion models point defects oxidation transient enhanced diffusion. Bhaskar Gadepally

13
**Session 2: Device Simulation**

Device models implemented in device TCAD tools: fundamentals of carrier transport drift-diffusion solution hydrodynamic solution carrier mobility models device physics of nanoscale technology inversion layer quantization fundamental limits of MOSFETs. Bhaskar Gadepally

14
**Session 3: Industry Application**

Introduction to process and device simulation tools. Mesh generation. Model selection. Predictive usage of TCAD: process model calibration device model calibration. Predictive simulation of CMOS technology. Bhaskar Gadepally

15
**Session 3: Industry Application - Calibration**

Calibration Effort TD Effectiveness Low Moderate High No or a limited calibration only provides some physical trends and is useful for a first-order process and device analysis. Global calibration provides higher accuracy and predictability of simulation data. Local calibration with the previous generation of technology will provide physical trends. Absolute values may not match real data. Bhaskar Gadepally

16
**Session 4: TCAD in Research & Modeling**

Simulation tools in device research: simulation structure model selection examples sub-100 nm MOSFETs DG-MOSFETs - FinFETs. TCAD in device (compact) modeling: substrate current model flash memory cell macro-model. Bhaskar Gadepally

17
**Technology CAD: Technology Modeling, Device Design and Simulation Bulk-Process Simulation**

2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India Samar Saha

18
**Outline Introduction. Bulk-process Models: Summary. Ion Implantation**

Diffusion Oxidation. Summary. Samar Saha

19
**Introduction Front-end IC fabrication processes include: p-substrate**

p-well n-well n+ PMOS p+ STI Gate oxide Halo P+ poly Spacer N+ poly NMOS (Shallow Trench Isolation) Source Drain Front-end IC fabrication processes include: implant: S/D and halo (low energy); well (high energy) etc. diffusion: Rapid thermal annealing (RTA) Þ Transient Enhanced Diffusion (TED) and other anomalous effects oxidation: gate oxide, STI liner oxide etc. Samar Saha

20
**Introduction Objective of this session:**

understanding of physical models implemented in a process TCAD tool model hierarchy model limitations building new models basic understanding of general purpose simulator internals TCAD models in general without considering any particular tools. Samar Saha

21
**Ion Implantation Ion Implantation Mechanisms. Ion Implant Models:**

Analytical Monte Carlo (MC). Implant-induced Damage Modeling. “Plus-one” Approximation. Summary. Samar Saha

22
Ion Implantation Bombard wafers with energetic ions energy, E 0.5 KeV - 1 MeV > Ebinding. Ions collide elastically with target atoms creating: ion deflections, energy loss displaced target atoms (recoils). Ions suffer inelastic drag force from target electrons ion energy loss lattice heating. Ion Target Recoil channeling Samar Saha

23
Ion Implantation Channeling is caused by ions traveling with few collisions and little drag along certain crystal directions. Ions come to rest after losing all the energy on: elastic collisions (nuclear stopping) inelastic drag (electronic stopping). Ion Target Recoil channeling Samar Saha

24
**Ion Energy Loss Mechanisms**

Nuclear stopping (Sn(E)): Deflected Ion Target Recoil q ion energy loss to target atom by interaction with the electric field of the target atom’s nucleus classical relationship of two colliding particles the scattering potential with the exponential screening function is given by where Z1 = atomic number of incoming ion Z2 = atomic number of target atom. Samar Saha

25
**Ion Energy Loss Mechanisms**

Electronic stopping (Se(E)) is due to the viscous drag force on moving ion in a dielectric medium. ke is a model parameter. Accurate model must account for the variation of Se in space. Stopping power S of an ion is given by: Samar Saha

26
**Ion Range Distribution**

Ions come to rest over a distribution of locations. Peak, depth, and lateral spread of distribution are determined by: ion mass, energy, dose, and incident angle target atom, composition, geometry, structure, and temperature. Implanted profile can be represented by: particles distribution functions. Samar Saha

27
**Ion Range Distribution**

Samar Saha

28
**Ion Range Distribution**

The as-implanted 1D distribution function is described by a series of coefficients called moments. 2D distribution of the implanted profile is constructed from 1D distribution function taking lateral spread » vertical spread. Samar Saha

29
**1D Analytical Ion Implantation Models**

Gaussian distribution: amorphous targets two coefficients where Q = implant dose (#/cm-2) Rp = projected range º normalized first moment sp = straggle/standard deviation º second moment. x Rp N Samar Saha

30
**1D Analytical Ion Implantation Models**

Pearson-IV: crystalline targets without channeling four coefficients (Rp, sp, skewness, kurtosis) crystalline targets with channeling, tilt, and rotation. six coefficients. Dual Pearson-IV: crystalline targets with channeling, tilt, and rotation second profile to model the channeling nine coefficients. Legendre Polynomials - 19 coefficients. Samar Saha

31
**1D Analytical Ion Implantation Models**

Coefficients are fit to the measured doping profiles. Coefficient-set for each distribution is tabulated for different: ion mass (As, B, In, P, Sb) dose, energy, tilt, and rotation target type. Multi-layer targets: each material is treated separately and scaled by its Rp. dose absorbed on the top layer is calculated and is used as the dose matching thickness for the layer below. Samar Saha

32
**2D/3D Analytical Ion Implantation Models**

Each 1D profile along a vertical line is converted to 2D or 3D distribution by multiplying it by a function of lateral coordinates: here lateral straggle, sl » sp Multi-layer targets and sloped surfaces are converted to 2D/3D by dose matching approach. More complex models have sl(x). Low energy profiles need non-separable point-response functions. Samar Saha

33
**Monte Carlo Modeling of Ion Implantation**

The collision energy loss is modeled by binary collision approximation (BCA), that is, each ion collides with one target atom at a time. The energy loss (DE) is modeled in terms of: incident energy, E0 and scattering angle, q0 of ion separation between two particles coulomb potential between two particles impact parameter. BCA requires special formulation for: ion channeling low energies when lattice movements come into play. Samar Saha

34
**Monte Carlo Modeling of Ion Implantation**

Ongoing development in MC modeling is to improve: speed of calculations electronic stopping power, Se model detailed local model for Se local and non-local split in energy loss due to Se where fnl = fraction of non-local energy split a = universal screening length p = impact parameter. Overall accuracy of MC implant model is excellent. Samar Saha

35
**Ion Channeling in Crystalline Silicon**

Along certain angles in crystal, ion may encounter no target atoms. Ion Repeated small-angle collisions steer the ion back into the channel. Channeling was first discovered by MC simulation. Channeling is: important at any energy critical at low energy where <110> channels steer Boron ions under MOS gate. Analytic channeling model is complex. Samar Saha

36
**Ion Channeling in Crystalline Silicon**

Samar Saha

37
**Damage Creation Models**

Each incoming ions generates damage seen by subsequent ions: recoils ® target atoms knocked out of lattice sites amorphous pockets. The effect of damage is significant on as-implanted profile as well as during subsequent diffusion. Models based on Kinchin-Pease formulation is used to estimate damage density: n = Er/2Ed where Er = recoil energy Ed = target displacement energy (~ 15 eV for Silicon). Samar Saha

38
**“Plus-one” Damage Model**

Most recoiled interstitials (I) find a vacancy (V) and recombine rapidly either during the implantation or the first instants of annealing. Distribution of remaining recoils shows: net excess of V near the surface net excess of I toward bulk. At low ion mass and/or moderate energy: population of net I and net V is less than the population of I due to dopant atoms taking substitutional sites one “extra-ion” is created for each dopant atom taking a substitutional site. Samar Saha

39
**Deviation from “Plus-one” Model**

“Plus-one” approximation often fails for: heavy ions as the population of recoils can become quite large relative to extra ion population low energy low dose. An effective “plus-n” factor as a function of ion species, energy, and dose is used. Typical values: As: n » E » 5 KeV; n » E » 500 KeV B: n » E » 5 KeV; n » 1.0 for E > 20 KeV P: n » E » 5 KeV; n » E » 500 KeV. Samar Saha

40
**Ion Implantation: Summary**

Ion implantation with ion energy > Ebinding of target atoms is used to implant impurity atoms into target. Analytical ion implantation model: the impurity profile is represented by moments for different species, dose, energy, tilt, and rotation the moments are extracted from the experimental profile to create look-up table simulation is performed using this look-up table. MC ion implantation model is more accurate, particularly for low energy. The implant damage is modeled by “plus-n” model. Samar Saha

41
**Diffusion Fundamentals of Dopant Diffusion Point Defect Model.**

Fick’s Laws Oxidation Enhanced Diffusion (OED) Oxidation Retarded Diffusion (ORD) Transient Enhanced Diffusion (TED). Point Defect Model. Clusters and Precipitates. Polysilicon Diffusion. Impurity Profiling. Summary. Samar Saha

42
**Fick’s Laws of Diffusion**

Fick’s first law: describes flux (F) through any surface diffusion is downhill - high ® low concentration, “- sign” Fick’s second law ® law of conservation of particles Low concentration diffusion in silicon is Fickian - each dopant A satisfies: (D º diffusivity = constant) Fin Fout Dx DC Samar Saha

43
**Concentration-Dependent Diffusion**

Typically, intrinsic carrier concentrations (ni) at processing temperatures are high » 1019 cm-3. For high doping concentrations, C > ni, dopant diffusion shows enhancements of the form: Diffusion enhancement is due to the variation of point defect population with Fermi level. The effective extrinsic diffusivity is given by: Samar Saha

44
**Surface Effects on Bulk Diffusion: OED/ORD**

Experimental data show that processes which modify the surface can affect diffusion in the bulk. Enhancement of diffusivity in one species while retardation in another is the evidence of two different diffusion mechanisms ® I and V. Samar Saha

45
**Transient Enhanced Diffusion (TED)**

Anomalous displacement of implanted dopants during low temperature anneals. Reverse temperature effect: displacement larger at lower temperatures - up to mm. Displacement increases with implant dose and energy. Corresponds to temporary increase in diffusivity ~ 10,000X. Implant of one species can drive diffusion of another. Enhancement is transient. Spatially non-uniform diffusion enhancements. Reduced activation. Samar Saha

46
**Transient Enhanced Diffusion (TED)**

As implanted over a buried B layer. As implant creates damage deep into the substrate. The implant damage causes a significant enhancement in B diffusion deep into the substrate during 20 sec. anneal at 850 °C. Simulation results Þ Samar Saha

47
**Point Defect Model for Dopant Diffusion**

Point defects (I and V) model explains: most of the observed trends in dopant diffusion by relating them to the properties of I and V “action-at-a-distance” effect of the surface on bulk diffusion. Vacancy mechanism As, Sb Kick-out mechanism B, P, In, As, Au, Zn, P above 900 °C Frank-Turnbull mechanism Zn, below 900 °C Samar Saha

48
Defect Charge States Defects which have states in the gap will have a distribution of charge states. The concentration of charged point defects depends on Fermi level. Dopants can diffuse with any of the defect charge states, some combinations have higher probability. In principle, must solve a set of: PDEs one for each combination. “Five-stream” diffusion model solves equations: “Three-stream” model solves equations. Samar Saha

49
**“Electric-field” Effects**

For high doping concentration > ni at the processing temperature, the electric field set up by ionized dopants affects diffusivity. Example: As + B co-diffusion at 900 °C, 15 min. Þ B- pulled towards the N+ region due to e-field effects. Samar Saha

50
**Generation/Recombination of Defects**

General flux model: where q = fraction of silicon atom injected Vm = silicon atom/cm3 assumed generation µ growth rate, G. recombination rate µ surface excess I - I* and increases under a growing surface. Lateral diffusion of defects during OED is governed by the ratio of DI/Kinert » 10 mm. Samar Saha

51
**Surface Generation/Recombination**

During OED, recombination/generation fluxes are large and must balance: Fixed interstitial super-saturations, also, occur under nitride, silicide surfaces. During TED, recombination appears to be fast, even at inert surfaces, recombination rate: Several models are available. Optimize Kinert for TED and adjust q to fit OED at the expense of lateral OED decay length. Samar Saha

52
**Gradient Effects in Transient Diffusion**

Dopant flux arises from diffusion of defects-dopant pairs: boron flux = DBIÑ[BI]. Number of pairs is proportional to the boron and interstitial concentrations: boron flux = DBIkpair(IÑB + BÑI) where IÑB = interstitials enhance boron diffusion ÑI = boron diffusion due to defect gradient During TED, ÑI is large near the surface causing: extra dopant flux to the surface surface pile-up (and possible interface loss) of dopant. Samar Saha

53
**Interstitial Clustering Model**

The growth and dissolution is given by: where kd is the decay constant kc is the growth constant C = concentration of clustered interstitials I = concentration of unclustered interstitials. After implantation I is large, dC/dt = C(kcI) Þ clusters grow exponentially until I = kd/kc. When I is small, clusters decay exponentially with time constant 1/kd. Samar Saha

54
**{311} Cluster Dissolution**

{311} defects: rod-shaped defect clusters condensed from “+1” amount of damaged silicon-I at annealing T > 400 °C precipitate on {311} planes and extend in the <110> directions to form planar defects. Time scale for {311} evaporation is similar to the time scale for TED. Simple reaction-based model offers first-order account of evaporation curve. Steady super saturation of dopant diffusion is observed during TED. Samar Saha

55
**Dopant Clustering/Precipitation**

Dopants are only soluble up to a limit at any temperature (solid solubility limit). Dopants also show deactivation below the solid solubility limit. Due to the clusters of size m dopant atoms such as As with m = 4, clustering reaction emits interstitials to generate required V. Can generate enhanced diffusion at the same level as TED. As V Samar Saha

56
Chemical Pump Effects Dopant atom A interacting with I form A + I « AI interstitial-assisted mobile species. When AI pairs diffuse out of a region of high I* to a region of low I*, pairs are out of equilibrium and must dissociate, AI ® A + I. A is deposited while I diffuses (“pumped”) away from the surface enhancing diffusion in bulk. Surface dopant layer may cause enhanced diffusion in bulk - e.g. D/D* = 70 at 900 °C. Causes cooperative diffusion, e.g. emitter push effect in bipolar junction transistors. Samar Saha

57
**Diffusion in Polysilicon**

Point defects usually pinned near equilibrium in poly due to grain boundaries. Dopants diffuse in two streams via grain and in boundary. An effective model includes: two streams dopant transfer from grain to grain boundary grain growth with time dopant transfer to grain boundary. Segregation coefficient, growth rate, and re-growth rate = f(temperature, grain size, Fermi level). Samar Saha

58
**Metrology for Developing Diffusion Models**

Spreading resistance profile (SRP) n 1D carrier profiles good sensitivity modest depth resolution carrier spilling difficult to use for shallow junctions. p Samar Saha

59
**Metrology for Developing Diffusion Models**

Secondary Ion Mass Spectroscopy (SIMS) 1D chemical profiles good sensitivity to all dopants excellent depth resolution surface region troublesome. 2D carrier profiling with excellent space resolution: scanning capacitance microscopy (SCM) measurement affects sample transmission electron holography (TEH) measures electrostatic potential difficult sample preparation. Samar Saha

60
**Monte Carlo Diffusion Methods: Algorithm**

Monte Carlo diffusion program (MARLOWE, UT-Austin) offers accurate diffusion modeling. MARLOWE Generates initial I, V positions THEORETICAL CALCULATIONS Energy of interactions and diffusion barriers EXPERIMENTS MONTE CARLO DIFFUSION CODE - Diffusion - Clustering - I - V recombination - Surface annihilation - I, V trapping - Boron kick-out, kick-in Samar Saha

61
Diffusion: Summary Diffusion is critical to activate the implanted dopants in the semiconductor devices. Dopants diffuse in silicon by interacting with point defects through a number of possible atomic-scale mechanisms. For short times, the diffusion is dominated by TED because of high concentration of point defects. Point defect concentrations depend on temperature, Fermi level, implant damage, and surface processes like oxidation. 1D/2D metrology is used to calibrate diffusion model. Samar Saha

62
**Oxidation Fundamentals of Thermal Oxidation. Oxide Growth Model:**

Deal-Grove Model Thin Oxide Model. Oxidation Chemistry. Oxide Flow: Oxidation-induced Stress Visco-elastic Model. Summary. Samar Saha

63
**Oxidation: Diffusion, Reaction, Flow**

Oxidation proceeds by three sequential processes: oxidant diffuses through existing oxide oxidant reacts at silicon surface to create new oxide overlying oxide flows to accommodate new volume. O2 or H2O ambient Oxidant Reaction zone Nitride Silicon Process is at first limited by reaction but diffusion through growing oxide becomes limiting. Samar Saha

64
**Oxidation: Deal-Grove Model**

C0 CL Silicon SiO2 Freac = kCL D = diffusivity of oxidant CL = concentration at Si-SiO2 interface C0 = concentration at the SiO2 surface L = oxide thickness k = interface reaction rate constant Samar Saha

65
**Oxidation: Deal-Grove Model**

C0 CL Silicon SiO2 Freac = kCL At equilibrium: Fdiff = Freac, \ CL = C0 / [1 + kL/D] Oxidation growth rate is given by: where C* = equil. oxidant conc.; Ns = # oxidant/cm3 in oxide Samar Saha

66
Thin Oxide Models Deal-Grove model does not fit the early part of oxidation curve. The data in thin regime can be fitted with an addition to Deal-Grove model given by: where and C0 » 3.6x108 mm/hr, EA » 2.35 eV, and l » 7 nm in <111> or <100> oriented silicon substrates. This model can be found in TCAD tools like SUPREM4. Samar Saha

67
**Oxidation - Planar Growth**

Planar growth generates an intrinsic stress in oxide during growth process: modest stress (3x109 dynes/cm2) density increases (< 3%) refractive index increases (1%) relative to fully relaxed oxides. First oxidation Second oxidation 1100 °C 800 °C 900 °C Two-step oxidation shows a significant difference in oxide density. DL grown in the second step varies depending on the thermal history of oxide (not just on L). Samar Saha

68
**Oxidation - Planar Growth**

Intrinsic stress is an atomistic process. Relaxes gradually with annealing at a rate which steadily decreases. Recent measurements show that relaxation rate is independent of stress level. History effects are not accounted for in most process simulators. Measured linear/parabolic coefficients describe oxidation in a state of intrinsic stress. 1D stress already accounted for in one-step oxidation. Samar Saha

69
Oxidation Chemistry Oxidation rate coefficients are sensitive to ambient additives: steam times faster than O2 3% Cl2 increases growth rate by % 100 ppm NF2 increases growth rate by 2 - 5 heavy substrate doping increases rate by according to the relation all easily accounted for by building table of B, B/A vs. additive or dopant concentration. NO, NO2 are not supported in most process TCAD tools. Samar Saha

70
**Oxide Flow Oxide growing on a curved surface must flow.**

Resulting deformations (and stresses) can be large! LOCOS top surface must stretch by %. Elastic limit of glass << 1% Silicon Old Oxide New Oxide Si3N4 Silicon Oxide Samar Saha

71
Oxide Flow Large deformations on a curved surface during oxidation mean viscous flow must occur. Viscous flow model used to model stress during oxide growth includes: incompressible viscous flow linear elasticity. Visco-elastic flow model: allows oxide to be “slightly” compressible eliminates pressure equation offers a significant numerical benefit. Samar Saha

72
**Visco-elastic Model: Stress Simulation**

Compression Tension SiO2 Si3N4 Oxide stress after local oxidation. Length of stress vector µ amount of stress. Samar Saha

73
**Oxidation: Summary Basic growth mechanism of thermal oxide:**

oxidant transport through the SiO2 layer to Si/SiO2 interface chemical reaction at the interface to produce the new layer of oxide. The growth is linear parabolic law. The basic Deal-Grove model is extended to explain: thin oxide growth mixed ambient oxidation. Important effects of thermal oxidation include OED, ORD, and impurity redistribution and segregation. Samar Saha

74
**Bulk-Process Simulation: Summary**

Accurate process models and TCAD tools are extremely critical for continuous scaling of IC’s . Workstation performance is continuously improving for cost-effective computer experiments. Existing models and TCAD tools treat different aspects of process simulation quite well. As new understanding develops, new models are incorporated in TCAD tools to improve predictability. Successful process TCAD will require a firm grasp of the controlling process physics. Samar Saha

75
**Technology CAD: Technology Modeling, Device Design and Simulation Device Simulation**

2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India Samar Saha

76
**Outline Introduction. Carrier Transport Models.**

Inversion Layer Mobility. Quantum Mechanical Confinement. Discrete Dopant Effects. Numerical Methods. Summary. Samar Saha

77
**Quasi-ballistic transport**

Introduction A device TCAD tool solves a set of equations to deal with various physical phenomena in semiconductor devices: p-substrate p-well n+ STI Poly hot carriers Non-local transport (velocity overshoot) QM tunneling Electrostatics: - 2D/3D effects - discrete charges Atomic scale effects QM confinement Surface scattering Quasi-ballistic transport Samar Saha

78
**Introduction Objectives of this session is to:**

focus on the underlying physics and models for practical application of device TCAD such as identify device physics issues for simulation discuss and compare simulation approaches identify limitations uncertainties challenges. Samar Saha

79
**Carrier Transport Models**

A device TCAD tool generates device characteristics by solving: Poisson’s [Ñ.D = r(r)] + carrier transport equations self-consistently. Carrier transport models include: drift-diffusion (DD) - standard Monte Carlo (MC) molecular dynamics hydrodynamic (HD) Boltzmann equation quantum balance equations. Samar Saha

80
**Carrier Transport Models**

The basic concept in transport theory is the carrier distribution function = f(r,px,t). f(r,px,t) = probability of a carrier at the position r with momentum px at any instant t. f(r,px,t) is a Maxwellian distribution function with: area = carrier density, n(r,t) the spread depends on carrier temperature f(r,px,t) px Equilibrium first moment is velocity second moment is kinetic energy. Samar Saha

81
**Carrier Transport Models**

f(r,px,t) px Equilibrium Non-equilibrium ex At equilibrium, f(r,px,t) is symmetric around px = 0. If an e-field is applied along the negative px direction: electron distribution is distorted and displaced from the origin causes electron scattering. Device TCAD challenge is to solve f(r,px,t). Samar Saha

82
**Carrier Transport Models**

To solve for f(r,p,t) - Boltzmann Transport Equation (BTE): six dimensions three in position space three in momentum space solution techniques: MC simulation spherical harmonics scattering matrix and so on. Samar Saha

83
**Carrier Transport Models**

Solving f(r,p,t), we can find the quantities that device engineers deal with directly such as: carrier density, n(r,t) current density, Jn(r,t) energy current, JE(r,t) average kinetic energy, un(r,t) electron temperature, Tn(r,t) heat flux, Qn(r,t). Six-dimensional equation is difficult to solve and computationally demanding. In TCAD, we directly solve for the quantities of interest. Samar Saha

84
**Carrier Transport: Balance Equations**

Basic idea to solve for a quantity (nf) of interest is to formulate a balance equation such as: rate of increase in nf = rate nf flows into the volume + net generation rate. Examples: nf = n(x,t): Þ continuity equation. nf = Jnx(x,t): Þ current equation. Samar Saha

85
**Carrier Transport Models**

Assuming slowly varying time, we can write the current equation: where t = average time between collisions m* = effective mass of electrons. We need a balance equation for kinetic energy, uxx. For simplicity of computation: approximate the effects of scattering in mn close the balance equations by approximating uxx. Samar Saha

86
**Carrier Transport Models: Drift-Diffusion**

The simplest solution of carrier transport equation is local field or DD approach. In DD, m is determined by scattering, scattering is determined by uxx, and uxx is determined by e. For high fields in bulk silicon, e(x) and uxx are constants or slowly varying: here mn = m0[N,TL,e(x)]; Dn = (kBTL/q)mn Then the current equation is given by: Þ Local field transport model: [mn = f(local field)] Samar Saha

87
**Carrier Transport Models: Drift-Diffusion**

DD solution fails to predict device characteristics for small geometry (£ 0.1 mm) MOSFETs. We know: here <t> is related to the average carrier energy, un(Tn) and Tn = local electron temperature. Thus, the DD-transport model can be improved by assuming, mn as a function of local energy. Local energy transport model: mn = f(local energy) Alternatively, mn = m0[N,TL,Tn] Samar Saha

88
**Carrier Transport Models: Local Energy**

Solve for energy density, nf = W(x,t) = nu: where tE = relaxation time. nf = JE(x,t): Unknowns: e(x), n(x), p(x), un(x), and up(x) increase in energy flux input e-field rate of energy dissipation Samar Saha

89
**Carrier Transport Models: DD vs. HD**

DD vs. HD model data deviate significantly for 40 nm devices. Samar Saha

90
**Macroscopic Transport Models: Summary**

Models are derived directly from BTE. Require numerous simplifying assumptions: closure, scattering. Difficult to assess the validity of assumptions. Many flavors: HD, energy transport (ET). Beyond DD, adds significant numerical complexity. HD/ET generally provide good estimates of: average carrier energy current density. Significant differences between various models. Samar Saha

91
**Carrier Transport Models: MC Simulation**

MC is a rigorous transport model. The essence of the model is: r1: free flight duration r2: scattering event r3: direction after scattering r4 electron r1 r2 r3, r4 Samar Saha

92
**MC Simulation: Summary**

Advantages: numerical method for solving the BTE with e-e correlation advanced physics is readily treated (e.g. scattering and complete band structures) most reliable transport method for treating hot electron distributions and for assessing novel devices. Disadvantage: computationally demanding: under near-equilibrium conditions for examining rare events. Samar Saha

93
**Carrier Transport Models: Quantum**

Different techniques available include: (1) equilibrium or ballistic transport simplest form is used for MOS capacitor simulation (2) wave propagation with phase randomizing scattering non equilibrium Green’s function approach (Wigner functions, density matrix) (3) density gradient/QM potential approach Samar Saha

94
**Carrier Transport Models: Summary**

Drift-diffusion (local field model): m = f(local field) Balance equations (mostly local energy): m = f(local energy) Examples: HD, ET, etc. Boltzmann solvers: MC Quantum transport: Schrodinger-Poisson density gradient / quantum potential. Samar Saha

95
**Inversion Layer Mobility**

Choice of mobility model can significantly alter the simulation results. Inversion layer mobility versus effective normal electric field show well- known characteristics: high fields: universal behavior independent of doping density. low fields: dependent on 1) doping density and 2) interface charge. universal behavior Samar Saha

96
**Inversion Layer Mobility**

Mobility versus effective normal electric field curve is modeled using three components: coulomb scattering (due to ionized impurity) phonon scattering - almost constant surface roughness scattering (at Si/SiO2 interface). At low normal fields: less inversion charge density ionized impurity scattering dominates and meff = f(NA). At high normal fields: higher inversion charge density close to the interface surface roughness scattering dominates. Samar Saha

97
**Inversion Layer Mobility**

For higher normal fields, universal behavior as a function of effective normal field: The effective field is a non-local quantity. Local field mobility models preferred for device TCAD should produce universal behavior in terms of the computed effective field. Example: Lombardi Surface Mobility Model. Samar Saha

98
**Inversion Layer Mobility**

For ultra-thin gate oxide thickness the inversion layer carrier wave function can extend through Si/SiO2 interface to SiO2/polysilicon interface. Mobility may depend on the surface roughness of SiO2/polysilicon interface “remote interface roughness” scattering. p-substrate p-well n+ STI NMOS Poly Gate Oxide Electron wave function Samar Saha

99
**Choice of Surface Mobility Models**

Samar Saha

100
**Inversion Layer Mobility: Summary**

Mobility is extremely critical for advanced MOSFET device simulation. Choice of mobility model can effect simulation data. Local field mobility models are being extended for high normal fields and high doping densities. New effects may begin to be felt in ultra-thin oxide devices Example: remote interface scattering. Samar Saha

101
**Quantum Mechanical Confinement**

The charges near the silicon surface are confined to a potential well formed by: oxide barrier bend Si-conduction band due to applied gate potential. Due to QM confinement of charges near the surface: energy levels are grouped in discrete energy sub-bands each sub-band corresponds to a quantized level for carrier motion in the normal direction. EC(y) Depth into Si (y) EF Energy Samar Saha

102
**Quantum Mechanical Confinement**

Due to QM confinement, the inversion layer concentration: peaks below the SiO2/Si interface » 0 at the interface and is determined by the boundary condition for the electron wave function. Depth into Si (y) n(y) Classical Quantum Dz Dz = shift in the centroid of charge in silicon away from the interface. Equivalent oxide thickness for Dz is: Samar Saha

103
**Quantum Mechanical Confinement**

Classical: CSi >> COX (accumulation / inversion) Ctotal ~ COX (accumulation / inversion) Quantum: CSi ~ eSi/Dz Ctotal < COX (accumulation / inversion) Impact of QM confinement: Vth since more band bending is required to populate the lowest sub-band TOXeff since a higher VG over-drive is required to produce a given level of inversion charge density Ctotal¯ since TOXeff = TOX + (eOX/eSi)Dz. Cox CSi Vgate Samar Saha

104
**QM Confinement: Modeling Approach**

van Dort’s model: amount of band-gap widening due to splitting of energy levels is given by: where B = constant y = distance from Si/SiO2 interface yref = reference distance for the material En = normal electrical field and, Samar Saha

105
**QM Confinement: Modeling Approach**

Modified local density approximation (MLDA): robust and efficient formulation to compute quantization of carrier concentration near Si/SiO2 interface offers a good compromise between the accuracy and simulation time the confined carrier density is given by FD statistics Samar Saha

106
**QM Confinement: COX Reduction**

Simulation data obtained by simulation program TSUPREM4 Samar Saha

107
**QM Confinement: TOX Measurement**

DTOX º TOXeff - TOX Samar Saha

108
**QM Confinement: Effect on Vth**

uniform 1e17 GR AR ST Nch (cm-3) Transition depth 1E18 1E17 GR-Graded Retrograde AR-Abrupt Depth Conventional Step, ST Vth increase due to QM effect depends on channel doping, Nch. Maximum increase in Vth ~ 100 mV for Nch ~ 1x1018 cm-3. Samar Saha

109
**QM Confinement: Effect on ION**

GR AR ST 1e18 uniform 1e17 Ion decrease due to QM confinement depends on Nch. Maximum drop in Ion~ 20% for Nch ~ 1x1018 cm-3. Samar Saha

110
**QM Confinement: Summary**

Impact of QM confinement becomes significant for TOX < 4 nm. QM confinement affects: TOX measurement drive current scaling limits. Modeling approaches: semi-physical (e.g. van Dort) quantum potentials - MLDA 1D self-consistent Schrodinger-Poisson. Samar Saha

111
**Discrete Dopant Effects**

The volume of active channel region for an advanced MOSFET: V = (W) x (L) x (Xj) Typically: length, L = 40 nm width, W = 100 nm; junction depth, Xj = 25 nm; Nchannel = 1x1018 cm-3 Ntot = 100 impurity atoms. V P (NA cm-3) Source Drain Xj Þ The number of dopants in V is a statistical quantity. Samar Saha

112
**Discrete Dopant Effects**

Effects of discrete dopants: significant threshold (Vth) variation, sVth (10’s of mV) lower average Vth (10’s of mV) asymmetry in drive current, IDS. Source Drain 3D transport leads to inhomogeneous conduction in sub-100 nm devices. Continuum diffusion models are inadequate to model discrete dopant effects in sub-100 nm MOSFETs. Samar Saha

113
**Discrete Dopant Effects: Summary**

2D continuum models can predict spread in Vth. Full 3D simulation is necessary to predict mean. The role of continuum versus granular models will become increasingly important as devices continue to shrink. Samar Saha

114
**Hot Electron Effects Effect: Outcome: Trends: hot electron injection.**

substrate current. Trends: power supplies are decreasing electric fields are increasing. Samar Saha

115
Hot-Carrier Effects Channel electron traveling through high electric field near the drain end can: Gate Ig n+ Drain n+ Source Isub m hole hot e- l become highly energetic, i.e. hot cause impact ionization and generate e- and holes holes go into the substrate creating substrate current, Isub. Some channel e- have enough energy to overcome the SiO2-Si energy barrier generating gate current, Ig. The maximum e-field, Em near the drain has the greatest control of hot carrier effects. Samar Saha

116
**Hot Electron Effects: Substrate Current**

Local field model (DD) ec = critical electrical field » 1.2 MV/cm a = impact ionization coefficient. calibration of impact ionization model parameters are required to match silicon data tuned parameter values can be non-physical and non-predictive for a new technology. Samar Saha

117
**Hot Electron Effects: Isub using DD Model**

DD simulation results with default Isub model parameters do not match the measurement data. Samar Saha

118
**Hot Electron Effects: Substrate Current**

Local energy model (HD / ET model) “surface impact ionization” better predictive capability than DD approach, but still uses tuned parameters. Non-local energy model. Full band MC. Samar Saha

119
**Hot Electron Effects: Summary**

Local field models are highly unphysical that result in unphysical calibrated parameters. Local energy models are more physical, but still require calibration of model parameters. Physically sound models that provide accurate results without calibration of model parameters are: full band MC non-local energy transport models. Samar Saha

120
Device TCAD: Summary As devices scale down to 0.1 mm and below, new physical effects are coming into play. Existing tools treat different aspects of device simulation fairly well. No single tool treats all of the important physics. Successful device TCAD will require a firm grasp of the controlling device physics. Samar Saha

121
Technology CAD: Technology Modeling, Device Design and Simulation Industry Application: Calibration of Process and Device Models 2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India Samar Saha

122
**Outline Objectives. Technology and Industry Trends affecting TCAD.**

TCAD Challenges. TCAD Tool Set. Calibration: Process Models Device Models. Mesh Generation. TCAD in Technology Development. Summary. Samar Saha

123
**Objectives Present issues and solutions for industrial TCAD:**

process simulation calibration device simulation key physical models mesh generation optimal approach calibration examples submicron process submicron device. Samar Saha

124
**Industry Trends affecting TCAD**

CMOS logic as technology driver: CMOS logic technology design-space much larger than that of DRAM or BJT technologies CMOS logic generation life-span is extremely short CMOS simulation is essentially 2D. Logic technology offerings becoming broader: high-Vth devices thick-oxide devices low-Vth devices. Samar Saha

125
**Industry Trends affecting TCAD**

System-on-a-chip (SOC) and logic derivatives: integration issues driving increasing share of TCAD cycles integrating memory and logic (NVRAM, DRAM) BiCMOS CMOS imaging SiGe BJT and PFET. Net result: Rapidly expanding opportunities for TCAD to contribute. Samar Saha

126
**Industry Trends affecting TCAD**

Rapid thermal processing (RTP): easy process addition Þ increases design space many subtle electrical effects. Larger wafer sizes: interaction of process variations on circuit performance becoming increasingly important Þ new TCAD arena. New impurity species Þ increase design options: In Ge N. Samar Saha

127
**Industry Trends affecting TCAD**

New materials and methods: nitrided gate oxide high-K gate dielectric junction pre-amorphization SOI selective epitaxial growth laser thermal annealing (LTA). Net result: rapidly expanding design space for TCAD to cover process TCAD challenges predominate. Samar Saha

128
**Industrial TCAD Challenges**

Challenge is to transform TCAD potential into valuable results for process and device engineers. Key tasks: system perspective connect process recipes to device parametric/circuit performance (“virtual fab”) organize TCAD process to make non-experts productive TCAD users and maximize productivity of experts process and device simulations process simulation reflect actual process results accurate electrical results for compact model extraction. Samar Saha

129
**Industrial TCAD Challenges**

Critical assumptions for success: calibrate/characterize complex physical models for the present range of operation - global calibration timely development/implementation of required physical models timely calibration (local calibration) of process and device models to contribute significantly for the next generation technology development technology transfer. TCAD usage can be significantly broadened. Samar Saha

130
**TCAD Tool Set Process simulation: 2D capability with examples based on**

extensive detailed physical model set for implantation, diffusion, oxidation, deposition, and etching detailed knowledge of model formulation and modification. examples based on vendor supported SUPREM4-process platform generalized calibration procedure. Samar Saha

131
**TCAD Tool Set Device Simulation:**

general 2D capability based on moments of Boltzmann equation control-volume discretization of DD/HD equations examples based on vendor supported MEDICI-device platform generalized calibration procedure user environment vendor supported TWB-framework platform. Samar Saha

132
**Calibration - Role of TCAD**

TCAD in research: evaluate advanced device options understand device physics. TCAD in technology development (TD): perform tradeoffs for design options to reduce experimental wafer starts assess manufacturability and design options diagnose device/layout problems. TCAD in manufacturing: process simplification for production technologies problem diagnosis and fix. Accuracy is crucial, especially, for TD and manufacturing. Samar Saha

133
**Need for Calibration Deviation of simulation and measured data:**

technology dependent: different focus area and application different physical models involved. site/fab dependent: equipment material environment measurement techniques human interface. Samar Saha

134
**Need for Calibration Limitation of physical models:**

secondary mechanisms become important model dependency on implementation details model short-fall in describing the target generation of process technology and devices. Limitation of model characterization/range: may not cover all possible process conditions may not cover all technologies may not be able to measure directly. Samar Saha

135
**Calibration Challenges**

Experimental data: expensive to obtain, especially, SIMS profiles insufficient processing information statistical fluctuations. Model complexity: some parameters can not be directly measured more parameters than data points. Simulation accuracy: grid dependency practical limitation on CPU and memory. Samar Saha

136
**Objective of Tool Calibration**

Device specific calibration: operation region (optimization) technology development items of importance. DOE and characterization. Calibration of model parameters. Supporting software utilities. Samar Saha

137
**General Calibration Methodology**

Use short flows to characterize process profiles: design process splits to cover design space. Use full flows to characterize devices with different dimensions (L and W dependencies). Tool calibration: match SIMS profiles use device data to correlate 2D effects match device characteristics. Two-phase process. Samar Saha

138
**Process Simulation Overview**

Model calibration for process simulation: overview of calibration process Phase 1: 1D impurity calibration methodology example - nMOSFET channel profile Phase 2: 2D calibration (process + device) example - reverse short channel effect (RSCE). Summary. Samar Saha

139
**Process Modeling Approach**

Predictive capability for a wide range of logic and memory technologies necessitates: new implant tables with new species like In, Ge etc. 3-stream TED model for dopant, interstitials, and vacancies “plus-n” damage model with accumulated damage from multiple implants amorphization due to implant damage transient activation/deactivation of dopants dislocation loops as source/sink for interstitials 3-phase segregation model. Samar Saha

140
**Process Simulation Calibration: Overview**

Model calibration (Phase 1) implant models diffusion models oxidation models etch/deposition models. TEM/SEM cross-sections, SIMS profiles, key (1D) electrical parameters. Technology/2D calibration (Phase 2) key process model parameters selected set of 2D electrical parameters. Samar Saha

141
**MOSFETs Process Model Calibration Flow**

Match SIMS profiles Adjust for dose loss Match Vth RSCE Two-dimensional Calibration DIBL Surface recombination Damage by S/D implant One-dimensional Calibration Implant moments/table OED Segregation (set by channel profile) Diffusivity (in oxide for dose loss) Tox (QM,Poly-depletion corrections) Diffusivity of dopant-defect pair Diffusivity of defects Samar Saha

142
**MOSFETs 1D Process Model Calibration**

p-substrate p-well n-well n+ PMOS p+ STI NMOS A B C F E D Cross-section for short loop experiments: A / D Þ NMOS / PMOS channel B / E Þ NMOS / PMOS SDE C / F Þ NMOS / PMOS S/D. Samar Saha

143
**A Typical Short Loop Experiment for P-Well**

Samar Saha

144
**Calibration Example: Channel Profile**

Use of detailed physical models to achieve 1D SIMS profile fit: typical Phase-1 calibration activity model updated over several technology generations. Channel profile after complete technology thermal cycle. Initial approach for implant and diffusion MC implant significant CPU burden scaled solid solubility physics-based implant moments / implant table update. Samar Saha

145
**Example: NMOS Channel Profile**

P-Well B, 200 KeV after spacer deposition/etch Depth (mm) log10 (Boron) SIMS Simulation Samar Saha

146
**Technology Calibration - Phase 2**

Coupled process and device simulations using Phase 1 calibration data. Target output (electrical) parameters: C - V curves Vth RSCE. Input variables (5 - 8 process model parameters): point-defect distributions from implants “plus-n” model key impurity segregation coefficients parabolic oxidation rate. Samar Saha

147
**2D Calibration Example: RSCE**

Samar Saha

148
**Process Modeling: Summary**

Systematic process model calibration methodology is critical. Observed success within a (CMOS) technology: process re-optimization offered a significant improvement in device performance process centering achieved at manufacturing co-location with minimum development effort. Observation: each successive technology generation requires a significant calibration effort (model update). Samar Saha

149
**Device TCAD Role of device simulation in TCAD**

Key physical models and examples: mobility models for deep sub-micron CMOS quantum effects in scaled CMOS devices DD model. Device model calibration: impact ionization with DD model. Summary. Samar Saha

150
**Device Simulation Role in TCAD**

Simulate device electrical behavior with sufficient accuracy to calibrate process simulation models: primarily 2D electrostatic simulation Vth, DIBL, Ioff, body effect, capacitances expect DD model is sufficient for most requirements for MOSFETs with Leff ³ 0.1 mm. Provide capability for the physical simulation of wide range of device parameters: substrate current, latch-up, ESD, and so on. Support exploratory device simulation for research. Samar Saha

151
**Device Simulation: CPU Burden**

Numerical issues associated with device simulation are well established: core issue is repeated solution of large, sparse, ill-conditioned, non-symmetric sets of linear equations typical industrial CMOS problem: ~ 10,000 mesh nodes simultaneous solution for (y, n, p) iterative solution methods often exhibit lack of convergence on problems of industrial interest. Optimized direct solution methods along with optimal mesh generation techniques can reduce CPU burden significantly without sacrificing accuracy. Samar Saha

152
**Critical TCAD Models: Carrier Mobility**

Device-design trends arising from CMOS scaling require consideration of: coulombic scattering in the inversion layer high substrate/channel doping levels channel doping can vary significantly across the device inversion- and accumulation-layer mobility. Industrial use of a mobility model requires: strictly local calculation of mobility minor increase in program complexity no restrictions on device geometries or device designs. Samar Saha

153
**Critical Device TCAD Models: QM Effects**

CMOS scaling requires inclusion of inversion-layer QM effects in device simulation for: thinner gate oxides higher substrate doping. Inversion-layer QM correction model must be: strictly local calculation of required physical quantities minor increase in program complexity no restrictions on device geometries or device designs acceptable CPU burden no significant degradation in robustness. Models: van Dort / MLDA. Samar Saha

154
**MOSFETs: Device Model Calibration Flow**

Work function QM model Low field mobility High field mobility Band to band tunneling Impact Ionization IDS vs. VGS (Vth) @ VBS = 0,VDS = 50 mV Isub vs. VGS @ VBS = 0,VGS = 0 IDS vs. VGS (IDS vs. VDS) @ VBS = 0,VDS = VDD IDS vs. VDS Samar Saha

155
**Example: Impact Ionization Model**

DD-simulation over estimates Isub by more than an order. Samar Saha

156
**Example: Impact Ionization Model**

Impact Ionization model calibration: used calibrated process model (technology calibration) used calibrated device models (device calibration) calibrate impact ionization coefficients. The electron impact ionization rate: where Ai and Bi are empirical constants Eeff = effective electric field due to non-local effect. Samar Saha

157
**Example: Impact Ionization Model**

For DD, transform the model in terms of local electric field, E. Assume, Eeff a E, Eeff = k * Eh where k and h are constants depending on the spatial variation of E near the drain-end of the channel. Substituting for Eeff and defining Bi º k * bih, the modified impact ionization coefficient is: \Optimize bi and h to fit the measurement data. Samar Saha

158
**Example: Impact Ionization Model**

Calibrate device TCAD models: comparison of I - V data. Samar Saha

159
**Example: Impact Ionization Model**

Simulation with calibrated impact ionization coefficients. Samar Saha

160
**Example: Impact Ionization Model**

Simulation with calibrated impact ionization coefficients. Samar Saha

161
Device TCAD: Summary Vendor supported device TCAD tools work very well with the present applications such as: MOSFET I - V and C - V characteristics for technology development logic DRAM. Model selection and calibration show good results for sub-0.25 mm technology development. Device TCAD effectiveness depends on: mobility model suitable for the target technology inversion-layer QM effects. Samar Saha

162
**Mesh Generation for Simulation**

Role and Requirements. Methods: structured quadtree unstructured hybrid. Example: typical MOSFET mesh and gridding considerations. Summary. Samar Saha

163
**Mesh Generation: Role and Requirements**

Requirement is to support complete automation of process-to-device simulation transition: highest barriers to expanded TCAD usage are mesh generation process simulation accuracy. Consistent and specialized grid distribution is an important key to simulation of high-performance MOSET devices: resolution of inversion layers and depletion regions resolution of mobility-model physical effects. Samar Saha

164
**Mesh Generation: Role and Requirements**

must accept device structures from detailed process simulation no restrictions on device structures mesh generation approach must minimize computational burden without compromising solution robustness and accuracy key: anisotropic grid-point distributions (the capability of supporting extreme differences in grid-point spacing in x- and y-directions). Samar Saha

165
**Mesh Generation Methods**

Samar Saha

166
**Hybrid Mesh Generation: Half-MOSFET**

x y Gate S/D Channel Source/Drain Samar Saha

167
Mesh Generation Dependence of device performance on vertical grid-spacing. Samar Saha

168
Mesh Generation Dependence of device performance on horizontal grid-spacing. Samar Saha

169
**Mesh Generation: Summary**

Mesh generation is the critical component of an effective TCAD system. Simulation results vary significantly on mesh and may result in: unphysical calibration parameters unpredictable/inconsistent results. Robust mesh: allows process simulators to be consistently and robustly linked to device simulators by non-experts significantly reduces CPU burden for device simulation. Samar Saha

170
**Industry Application: Summary**

Vendor supported TCAD tools offer most simulation capabilities for industrial usage. Systematic calibration procedure is required to support efficient: process technology optimization future technology development. Mesh generation is crucial for predictive technology simulation. Well calibrated physical models provide efficient predictive TCAD capability. Samar Saha

171
Technology CAD: Technology Modeling, Device Design and Simulation Industry Application: TCAD in Device Research and Compact Modeling 2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India Samar Saha

172
**Research Application: Overview**

Role of TCAD in device research: how it differs from development/manufacturing. examples sub-100 nm MOSFET device design design optimization of FinFETs. TCAD for compact modeling: TCAD-based compact model parameter extraction for substrate current modeling flash memory cell macro model. Summary. Samar Saha

173
**Role of TCAD in Research**

Performance analysis of future device design options to guide development effort. Understand device physics for new device concepts. Typically, research TCAD is not the “virtual fab” paradigm: process simulation is not used, since device cannot be made with current process technologies. Circuit performance is directly evaluated from the output of device simulation using two different ways: device simulation Þ model extraction Þ circuit simulation mixed-mode device/circuit simulation. Samar Saha

174
**Example: Sub-100 nm MOSFET Design**

Design issues in achieving MOSFET devices near the lower limit of channel length: scaling requirements material limitations of scaling feasibility of continuous scaling. Methodology to generate sub-100 nm MOSFET device characteristics vs. scaling parameters. Results and discussions. Summary. Samar Saha

175
**Scaling Requirements vs. Limitations**

Samar Saha

176
**Feasibility of Continuous TOX and Xj Scaling**

Scaling Tox(eff) < 2 nm is feasible with a high-K dielectric gate material to maintain: a thicker value of TOX(physical) for a tolerable value of Lg a target value of gate capacitance (COX) equivalent to that of an ultra-thin SiO2 gate material. Scaling Xj < 30 nm is essential to: scale down Lg, gate area, and COX improve ac device performance. Samar Saha

177
**Idealized Device Simulation Structure**

Leff Halo Xjd Xj DSD SDE Lext TOX Lg Body (B) Poly-Si gate Spacer Channel doping profile: vertically and laterally non-uniform. SDE: heavily-doped source-drain extension regions with junction depth Xj. DSD: heavily-doped deep source-drain of junction depth Xjd. Halo: channel-type doping around SDE regions. Samar Saha

178
**Design Simulation Experiment**

Designed CMOS technologies for Leff = 25 nm with: {Lg = 40 nm, 14 nm, Tox(eff) = {1,1.5, 2} nm} {Lg = 50 nm, 20 nm, Tox(eff) = {1,1.5, 2} nm} {Lg = 60 nm, 26 nm, Tox(eff) = {1,1.5, 2} nm}. For each technology: non-uniform vertical channel doping profile was optimized for the target long channel 0.23 V two halo profiles (double halo architecture) were used to reduce DIBL from both SDE and DSD regions achieve non-uniform lateral channel doping profile with the target 10 |VDD| = 1 V. Samar Saha

179
**Simulation Strategy Optimized technology parameters:**

SDE peak 2.5x1020 cm-3 DSD peak 3.7x1020 cm-3 peak halo 5x x1019 cm-3. Channel concentration ® dependent on Lg. Device characteristics were generated using MEDICI with: hydrodynamic model for semiconductors van Dort’s Quantum Mechanical model calibrated device models (global calibration!!). Samar Saha

180
**Simulated Channel Doping Contours**

Lg Samar Saha

181
**Simulated Vth vs. Leff for different TOX(eff)**

|Vth| increases with the increase in TOX(eff) for all devices. Devices with Leff = 25 nm and TOX(eff) = 2 nm, |Vth| > 0.4 V is too high for high-performance |VDD| £ 1 V. TOX(eff) < 2 nm offers lower |Vth| for low power operation. Samar Saha

182
**Simulated IDSAT vs. Ioff for different TOX(eff)**

Devices with 10 nA/mm represents Leff = 25 nm. At a constant |Ioff| ³ 2 nA/mm: |IDSAT| increases as TOX(eff) decreases TOX(eff) < 2 nm is essential to improve IDSAT for Leff = 25 nm devices. Samar Saha

183
**Simulated I - V Data for TOX(eff) = 1 nm**

For a typical 50 nm technology with Leff = 25 nm and Tox(eff) = 1 nm: 80 mV/decade 60 mV 680 mA/mm, 275 |VGS| = 1 V = |VDS|. Samar Saha

184
**Simulated I - V Data for TOX(eff) = 1.5 nm**

For 25 nm devices of a 50 nm CMOS technology, as Tox(eff) increases from 1 nm ® 1.5 nm: S increases 8 mV/decade] DIBL increases 30 mV] |IDSAT| decreases 102 mA/mm; 42 mA/mm]. Samar Saha

185
**Simulated I - V Data for TOX(eff) = 2 nm**

For 25 nm devices of a 50 nm CMOS technology, as Tox(eff) increases from 1 nm ® 2 nm: S increases 16 mV/decade] DIBL increases 60 mV] |IDSAT| decreases 214 mA/mm; 72 mA/mm]. Samar Saha

186
**Simulated Vth vs. Xj for Different TOX(eff)**

Samar Saha

187
**Simulated IDSAT vs. Xj for Different TOX(eff)**

Samar Saha

188
**Simulated DIBL vs. Xj for Different TOX(eff)**

Samar Saha

189
**Simulated S vs. Xj for Different TOX(eff)**

Samar Saha

190
**Simulated Delay for Different Xj and Lg**

Samar Saha

191
**Sub-100 nm MOSFET Design: Summary**

The simulation results show the feasibility of 25 nm MOSFETs with: TOX(eff) < 2 nm to maintain lower |Vth| for |VDD| £ 1 V operation achieve higher |IDSAT| for a target value of |Ioff| lower value of DIBL lower value of 80 mV/decade Xj < 30 nm to scale Lg < 60 nm improve device speed. 25 nm devices with 14 nm and 40 nm show a significant improvement in speed. Samar Saha

192
**Example: Double Gate MOSFET Design**

Design FinFET (double-gate MOSFET) Simulation Structure. Optimize Different Fin-dimensions. Feasibility of 20 nm FinFET Device. Comparison of 20 nm Device Performance using FinFET vs. Conventional MOSFET Architecture. Summary. Samar Saha

193
**Idealized Double Gate MOSFET Structure**

Tox TSi Source Drain Top Gate Bottom Gate Lg Tox = Top/bottom gate oxide thickness. TSi = Un-doped/lightly-doped channel width. Lg = Channel length. Samar Saha

194
**Simulated DG-MOSFET FinFET Structure**

Hfin Lg Samar Saha

195
**Major Process Steps to Generate FinFETs**

1. Define Si-Fin 2. Gate oxidation 3. Poly-Si gate 4. Nitride spacer S/D implant 5. Half-structure 6. Full-structure Oxide Si-Fin BOX Nitride Poly Samar Saha

196
**Critical Parameters for FinFET Simulation**

Parameters used for simulation structure design: Tfin = 10 to 30 nm Hfin = 50 nm Lg = 10 to 50 nm Tox = 1.5 nm. For device simulation, channel doping was optimized to obtain 0.1 V for Lg = 20 nm nFinFETs. Device structures and the characteristics were generated using 3D-simulation tool Taurus (from Synopsys). Samar Saha

197
**Vth vs. Lg for Different Tfin; Hfin = 50 nm**

Samar Saha

198
**IDSAT vs. Lg for Different Tfin; Hfin = 50 nm**

Samar Saha

199
**S vs. Lg for Different Tfin; Hfin = 50 nm**

Samar Saha

200
**I - V Characteristics of 20 nm FinFETs**

Samar Saha

201
**FinFETs vs. Conventional MOSFETs**

20 nm FinFETs show superior device performance compared to 20 nm conventional MOSFETs. Samar Saha

202
**FinFET Design: Summary**

TCAD is used to design and study FinFET device characteristics. The simulation data for nFinFETs with 10 nm < Lg < 50 nm and Hfin = 50 nm show: higher Vth roll-off as Lg decreases for thicker Tfin devices lower IDSAT in thinner Tfin devices due to higher s/d resistance increase in S with decrease in Lg for Tfin < 50-nm S ® 60 mV/decade for all Tfin with Lg >>40-nm. 20 nm FinFETs show superior device performance than 20 nm conventional bulk-MOSFETs. Samar Saha

203
**Example: Compact Model Extraction for Isub**

Procedure for TCAD-based Compact Model Parameter Extraction. Simplification of Isub Model for TCAD-based Compact Modeling. Model Extraction. Model Verification. Summary. Samar Saha

204
**Substrate Current, Isub Model**

Isub generated due to impact ionization is given by: where Ai and Bi are impact ionization parameters lc = characteristic length of saturation region Em = maximum lateral electric field near the drain Ec = critical electric field for velocity saturation. Samar Saha

205
**Substrate Current, Isub Model**

At strong inversion (VDS >> VDSAT) Em is given by: where Leff = effective channel length of device Vth = threshold voltage of device. Samar Saha

206
**Substrate Current, Isub Model**

The bias dependence of Ec is given by: Ec = Ec0 + EcgVGS + EcbVBS where Ec0, Ecg, and Ecb are model parameters given by: Ec0 = VGS = VBS = 0 Ecg = slope of Ec vs. VGS VBS = constant Ecb = slope of Ec vs. VBS VGS = constant The bias dependence of lc is given by: lc = (lc0 + lc1VDS)ÖTOX here lc0 and lc1 are model parameters. Samar Saha

207
**Isub Model Parameters Empirical constants:**

Ai = 1.65x106 (1/cm) Bi = 1.66x106 (V/cm) Technology dependent parameters: Ec0 = bias independent constant (V/cm) Ecg= gate bias dependent parameter (1/cm) Ecb = back-gate bias dependent parameter (1/cm) lc0 = bias independent constant (Öcm) lc1 = bias dependent constant (Öcm/V). We assume, lc = lc0 is a technology dependent constant for TCAD-based parameter extraction (i.e. ignore lc1). Samar Saha

208
**TCAD-based Isub Model Extraction**

VDSAT extraction Ec extraction lc extraction SPICE simulation Format I - V data Compute Isub/IDS Device Simulation Device Model Calibration At each VGS, generate: IDS - VDS and Isub - VDS Process Process Model Generate: Device Structure Extraction of {Ec0, Ecg, Ecb} Samar Saha

209
**Parameter Extraction: VDSAT**

VDSAT is extracted by mapping constant Isub/IDS contours on IDS vs. VDS family of simulated curves. Samar Saha

210
**Parameter Extraction: Ec0, Ecg, and Ecb**

Ec0 and Ecg extraction: extract VDSAT for different values of VGS at VBS = 0. compute Ec from: plot Ec vs. VGS to extract: Ec0 = VGS = 0 Ecg = slope. Same procedure to extract Ecb with VBS ¹ 0. Samar Saha

211
**Parameter Extraction: lc and Components**

The simplified from of the expression: log(Y) = mX + C, where X = 1/(VDS - VDSAT) Y = Isub/[IDS(VDS - VDSAT)] Parameters are extracted from log(Y) vs. X plots: slope, m = - Bi lc intercept, C = ln(Ai/Bi). Samar Saha

212
**Parameter Extraction: lc and Components**

Samar Saha

213
**TCAD-based Isub Models**

For nMOSFET devices of the target technology: Ec0 = 5.50E+04 (V/cm) Ecg = 3.50E+03 (1/cm) lc = 1.38E-05 (cm) Ai = 1.65E+06 (1/cm) Bi = 1.66E+06 (V/cm) Samar Saha

214
Model Verification Measurement and simulation data using the extracted models. Samar Saha

215
Model Verification Measurement and simulation data using the extracted models. Samar Saha

216
**Model Extraction for Isub: Summary**

The example shows the basic idea to use TCAD for compact model parameter extraction using: calibrated process models for process TCAD calibrated device models for device TCAD simplified equations and extraction routines, as needed. Process and device models were calibrated for the target technology. Isub model is simplified to extract model parameters. The simulation data using TCAD-based model agree very well with the measurement data. Samar Saha

217
**Example: Flash Memory Cell - Macro Model**

Flash Memory Cell Compact Modeling split gate cell two-transistor macro model necessity for TCAD-based macro model. Model extraction. procedure. Samar Saha

218
**Flash Memory Cell - Split Gate Structure**

Cell consists of: WL transistor FG transistor. FG may not have contact pad for measurement. Typically, 1T-cell model is used. 2T-model provides more accurate cell characteristics. TCAD-based. Samar Saha

219
**Flash Memory Cell: TCAD-based Model**

Calibrated Device Model Process Model Extract SPICE Model for T1 Model for T2 Model Verification Simulate I - V for T1 Test Structures SPICE/Circuit Simulation Generate Macro Model I - V for T2 Samar Saha

220
**TCAD in Research & Modeling: Summary**

Device TCAD can be successfully used in device research to: study different device options examine new device ideas optimize device design range for technology development guideline. Calibrated TCAD models can be used accurately to: predict device performance extract compact model predict circuit performance. Samar Saha

221
References [1] J.D. Plummer et al., Silicon VLSI Technology - Fundamentals, Practice and Modeling. Prentice Hall, New Jersey, 2002. [2] S. Tian, “Predictive Monte Carlo ion implantation simulator from sub-keV to above 10 MeV,” J. Appl. Phys., vol. 93, No. 10, p 5893, 2003. [3] S. Furukawa et al., “Theoretical considerations on lateral spread of implanted ions,” Jap. J. Appl. Phys., vol. 11, p 134, 1992. [4] S. Hobler and S. Selberherr, “Two-dimensional modeling of ion implantation induced point defects,” IEEE Trans. Computer-Aided Design, vol. 7, p 174, 1998. [5] L. Pelaz et al., “Modeling of the ion mass effect on transient enhanced diffusion: deviation from ‘+1’ model,” Appl. Physics. Lett., vol. 73, p 1421, 1998. [6] S. Chakravarthi and S.T. Dunham, “Influence of extended defect models on prediction of boron transient enhanced diffusion,” in Silicon Front End Technology - Materials Processing and Modeling, N. Cowern, P. Griffin, D. Jacobsen, P. Packan, and R. Webb, eds. (Mat. Res. Soc. Proc. vol. 532, Pittsburgh, PA, 1998). Samar Saha

222
References [7] P.M. Fahey et al., “Point Defects and Dopant Diffusion in Silicon,” Rev. Modern Physics, vol. 61, p. 289, 1989. [8] A. S. Grove, Physics and Technology of Semiconductor Devices. John Wiley & Sons, New York, 1967. [9] H.Z. Massoud et al., “Thermal Oxidation of Silicon in Dry Oxygen: Growth-Rate Enhancement in the Thin Regime I. Experimental Results, II Physical Mechanisms,” J. Electrochem. Soc., vol. 132, p and 2693, 1985. [10] F. Nouri et al., “Optimized shallow trench isolation for sub-0.18 mm technology,” Proc. SPIE Conf. on Microelectronic Device Technology, vol. 3506, p. 156, 1998. [11] TSUPREM4, Synopsys Corp., Mountain View, CA. [12] H. Kosina et al., Device modeling for the 1990’s,” Microelectron. J., vol. 26, p. 217, 1995. [13] S.E. Laux and M.V. Fischetti, “Transport models for advanced device simulation-truth or consequences?,” BCTM Tech. Dig., 1995. Samar Saha

223
References [14] M.K. Ieong and T.W. Tang, “Influence of hydrodynamic models on the prediction of semiconductor device characteristics,” IEEE-TED, vol. 44, p. 2242, 1997. [15] M.S. Lundstrom, Fundamentals of carrier transport, 2nd edition Cambridge University Press, 2000. [16] M.N. Darwish et al., “An improved electron and hole mobility model for general purpose device simulation,” IEEE-TED, vol. 44, p. 1529, 1998. [17] D. Vasileska et al., “Scaled silicon MOSFETs: Degradation of the total gate capacitance,” IEEE-TED, vol. 44, p. 584, 1997. [18] C. Rafferty et al., “Multi-dimensional quantum effect simulation using a density-gradient model and script-level programming techniques,” Simulation of Semiconductor Process and Devices, K.De Meyer and S Biesemans (eds.), p. 137, 1998, Springer-Verlag. [19] M.J. van Dort et al., “A simple model for quantization effects in heavily-doped silicon MOSFETs at inversion conditions,” Solid-St. Electron., vol. 37, p. 411, 1994. Samar Saha

224
References [20] P. Vande Voorde et al., “Accurate doping profile determination using TED/QM models extendible to sub-quarter micron nMOSFETs,” IEDM Tech. Dig., p. 811, 1996. [21] S. Selberherr, “MOS device modeling at 77K,” IEEE-TED, vol. 36, p.1464, 1989. [22] S. Saha, “Effects of inversion layer quantization on channel profile engineering for nMOSFETs with 0.1 mm channel lengths,” Solid-State Electron., vol. 42, p. 1985, 1998. [23] S. Saha et al., “Effects of inversion layer quantization and polysilicon gate depletion on tunneling current of ultra-thin SiO2 gate material,” Mater. Res. Soc. Symp. Proc., vol. 567, p. 275, 1999. [24] P. Wong and Y. Taur, “Three-dimensional atomistic simulation of discrete random dopant distribution effects in sub-0.1 mm MOSFETs,” IEDM Tech. Dig., p. 705, 1993. [25] P.A. Stolk et al., “Modeling statistical dopant fluctuations in MOS Transistors,” IEEE-TED, vol. 45, p. 1960, 1998. Samar Saha

225
References [26] S.E. Laux and M.V. Fischetti, “The physics of hot-electron degradation of Si MOSFETs: can we understand it?,” App. Surf. Sci., vol. 39, p. 578, 1989. [27] C. Jungemann et al., “Is physically sound and predictive modeling of NMOS substrate currents possible?,” Solid-St. Electron., vol. 42, p. 647, 1998. [28] S. Saha et al., “Impact ionization rate of electrons for accurate simulation of substrate current in submicron devices,” Solid-State Electron., vol. 36, p. 1429, 1993. [29] R.W. Dutton and Z. Yu, Technology CAD: Computer simulation of IC processes and devices. Kluwer, 1993. [30] S. Selberherr, Analysis and simulation of semiconductor devices. Springer-Verlag, 1984. [31] N. Arora, MOSFET models for VLSI circuit simulation – theory and practice. Springer-Verlag, 1993. [32] S. Saha, “Managing technology CAD for competitive advantage: An efficient approach for integrated circuit fabrication technology development,” IEEE Trans. Eng. Manage., vol. 46, p. 221, 1999. Samar Saha

226
References [33] S. Saha, “Improving the efficiency and effectiveness of IC manufacturing technology development,” in Technology and Innovation Management, D.F. Kocaoglu, T.R. Anderson, D.Z. Milosevic, K. Niwa, and H. Tschirky (eds.), Portland, OR: PICMET 1999, p. 540, 1999. [34] S. Saha, “Technology CAD for integrated circuit fabrication technology development and technology transfer,” in Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing II, vol. 5042, p. 63, 2003. [35] C.V. Mouli, “Models and methods: Effective use of technology-computer aided design in the industry,” J. Vac. Sci. Tech. B., vol. 18, p. 354, 2000. [36] C. Lombardi et al., “A physically based mobility model for numerical simulation of non-planar devices,” IEEE Trans. Computer-Aided Design., vol. 17, p. 1164, 1988. [37] S. Saha, “MOSFET test structures for two-dimensional device simulation,” Solid-State Electron., vol. 38, p. 69, 1995. [38] O.C. Zienkiewcz, The Finite Element Method, McGraw-Hill, 1977. Samar Saha

227
References [39] S. Saha, “Scaling considerations for high performance 25 nm metal-oxide-semiconductor field-effect transistors,” J. Vac. Sci. Tech.. B, vol. 19, p. 2240, 2001. [40] S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State Electron., vol. 45, p. 1851, 2001. [41] C.C. Hu, “FinFET – a device for nanoscale IC (NSI),” in IEEE Silicon Nanoelectronics Workshop Digest, p. 1, 2002. [42] S. Saha, “Device characteristics of sub-20 nm silicon nanotransistors,” in Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing II, vol. 5042, p. 172, 2003. [43] G. Pei et al., “FinFET design consideration based on 3-d simulation and analytical modeling,” IEEE Trans. Electron. Dev., vol. 49, p.1411, 2002. [44] TAURUS, Synopsys Corp., Mountain View, CA. [45] MEDICI, Synopsys Corp., Mountain View, CA. [46] S. Saha, “Extraction of substrate current model parameters from device simulation,” Solid-State Electron., vol. 37, p. 1786, 1994. Samar Saha

Similar presentations

OK

EE415 VLSI Design The Devices: Diode [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design The Devices: Diode [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on standardization and grading Ppt on human chromosomes chart Ppt on formation of company Download ppt on 4 p's of marketing Ppt on lifelines of national economy for class 10 Training ppt on iso 9001 Ppt on refraction of light through prism Ppt on digital advertising Ppt on contact management system Ppt on abortion