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Is Dual Gate Device Structure Better From a Thermal Perspective? D. Vasileska, K. Raleva and S. M. Goodnick Arizona State University Tempe, AZ USA.

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Presentation on theme: "Is Dual Gate Device Structure Better From a Thermal Perspective? D. Vasileska, K. Raleva and S. M. Goodnick Arizona State University Tempe, AZ USA."— Presentation transcript:

1 Is Dual Gate Device Structure Better From a Thermal Perspective? D. Vasileska, K. Raleva and S. M. Goodnick Arizona State University Tempe, AZ USA

2 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Technology Trends and Device Miniaturization Solutions

3 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Why Heating Effects in Alternative Device Geometries? dSdS ~ 300nm

4 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Complexity of the Problem: Treatment of Phonons

5 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics ASU Solution J. Lai and A. Majumdar, Concurent thermal and electrical modeling of submicrometer silicon devices, J. Appl. Phys., Vol. 79, 7353 (1996).

6 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Thermal EMC Device Simulator Initialize Calculate Scattering Table Free-flight scatter Check contacts Solve Poisson Current Convergence Solve Phonon Energy Balance Equations Exchange of Variables

7 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics The Role of Velocity Overshoot: Less Current Degradation 25 nm Channel Length Device

8 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Longer Channel Devices Affected More Hot-Spot Moves Towards the Channel for Larger Devices Acoustic Phonon Temperature

9 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Can We Further Minimize Lattice Heating Problems in Nanodevices? OUR ALTERNATIVES: Dual Gate Devices

10 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Double-Gate SOI: From Electrical Perspective + Enhanced SCE scalability + Lower junction capacitance + Light doping possible + Vt can be set by WF of metal gate electrode + ~2x drive current - ~2x gate capacitance - High R series,s/d raised S/D - Complex process T si, Ultra- thin Body, Fully Depleted SD Top Bottom Double-Gate SOI: BOX SUBSTRATE

11 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Double-Gate SOI: From Thermal Perspective Higher Number of Carriers Higher Lattice Temperature More Velocity Degradation

12 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics A Closer Look … Single gate lattice temperature profile Dual gate lattice temperature profile

13 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics Where Does the Benefit of the DG Structure Comes From? 25nm DG SOI nMOSFET (Vgate-top=Vgate-bottom=1.2V; Vdrain=1.2V; Vsource=0V; Vsubstrate=0V) Type of simulation Top gate temperature Bottom gate temperature Bottom of the BOX temperature Current (mA/um) Current decrease (%) isothermal300K \ thermal300K thermal400K 300K thermal600K 300K Type of simulation Gate temperatur e Bottom of the BOX temperatur e Current (mA/um) Current decrease (%) isothermal300K \ thermal300K thermal400K300K thermal600K300K N D =10 19 cm -3 ; N A = cm -3 t ox =2nm; t si =10nm; t BOX =50nm 25nm FD SOI nMOSFET 25nm DG SOI nMOSFET For almost the same Current degradation DG devices offer times more current

14 Ira A. Fulton School of Engineering AINE – Arizona Institute for Nanoelectronics What Needs to be Done in Terms of Modeling Thermal Effects? When the heat conduction is nonlocal, the transport is highly nonequilibrium, the temperature used to represent the modeling results is at best a measure of the local energy density, rather than their typical thermodynamic meaning. When the heat conduction is nonlocal, the transport is highly nonequilibrium, the temperature used to represent the modeling results is at best a measure of the local energy density, rather than their typical thermodynamic meaning. On the other hand, in microelectronics, the device reliability is often associated with the temperature through the Arrehnius law, which is a manifestation of the Boltzmann distribution and is a result obtained under the assumption of local equilibrium. On the other hand, in microelectronics, the device reliability is often associated with the temperature through the Arrehnius law, which is a manifestation of the Boltzmann distribution and is a result obtained under the assumption of local equilibrium. The simulations so far are based on either Monte Carlo methods or the Boltzmann equation and take the various relaxation times as input parameters. These parameters are subject to a wide range of uncertainties. The simulations so far are based on either Monte Carlo methods or the Boltzmann equation and take the various relaxation times as input parameters. These parameters are subject to a wide range of uncertainties. There is a clear need for more accurate information on the relaxation times. Molecular dynamics simulation may be one way to obtain them. There is a clear need for more accurate information on the relaxation times. Molecular dynamics simulation may be one way to obtain them. Similarly, electron-phonon scattering processes also need further consideration, particularly when electrons have very different temperatures from that of phonons. Similarly, electron-phonon scattering processes also need further consideration, particularly when electrons have very different temperatures from that of phonons.


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