Presentation on theme: "TMS320DM365 Stephanie Evans DM3x Marketing Manager, Texas Instruments Embargoed until March 3, 2009."— Presentation transcript:
TMS320DM365 Stephanie Evans DM3x Marketing Manager, Texas Instruments Embargoed until March 3, 2009
2 Integrated Image Signal Processing (ISP) Multi-format, multi-rate, multi-stream, multi-channel Production-ready codec bundles Pixel-perfect 1080p HD video flexibility Multi-format HD video with H.264 up to 1080p H.264, MPEG-4, MPEG-2, MJPEG & VC1 Up to 25% system cost savings Peripheral integration ISP eliminates use of expensive optics Flexibility without complexity Auto white balance Auto focus Auto exposure Face detection Noise filtering Video stabilizer Edge enhancement 1080p H.264 at 10 fps optimized for video surveillance 1080p MPEG-4 at 24 fps 720p H.264, MPEG-4 at 30 fps EMAC, USB 2.0, RTC, DDR2...
3 IP security camera Multi-format HD video jumpstarts camera- and playback- driven designs H p at 10 fps Baby monitor MPEG-4 at 1080p H.264 at 720p Video doorbell MPEG-4 at 1080p H.264 at 720p HD web cam MPEG-4 at 1080p H.264 at 720p Personal media player MPEG-4 at 1080p H.264 at 720p MPEG-2, VC1 Digital signage MPEG-4 at 1080p H.264 at 720p Multi-channel DVR MPEG-4 at 1080p H.264 at 720p HD multi-format video Advanced image processing Multimedia Connectivity
4 Peripherals ARM Subsystem ARM9 CPU 300 MHz DMA Data & Configuration Bus Program/Data Storage SystemConnectivity Serial Interfaces ASP x2 Image Signal Processing (ISP) Enhanced On-Screen Display 10b HD/SD DAC Video Enc Video Processing Subsystem Back End Front End EDMA HMJCP Co- Processor H.264 VC1 MPEG2 MPEG4 JPEG SPI x3 I2CI2C UART x2 HPI Voice Codec RTC Keyscan/ADC 10b HD/SD DAC DM365 digital media processor Multi-format video - HD H.264 / MPEG-4 / VC1 video Performance 1080p 10fps - H p 30fps (encode/universal decode) –H.264 HP –MPEG4 SP –MPEG2 –WMV9/ VC-1 AP JPEG encode/decode at 50 MPixels/second Features Core –ARM926EJ-S core, 300 MHz –H.264, MPEG-4 & JPEG coprocessor (HMJCP) –Video Processing Subsystem (VPSS) Memory –ARM: 16KB I-Cache; 8KB D-Cache; 8KB ROM; 32KB program/data Peripheral Highlights –EMAC 10/100 –USB 2.0 HS OTG device and mini-host w/ PHY –External Memory Interface (EMIF) –Mobile DDR/DDR2 –HPI –Keyscan/ADC –Audio Voice Codec Package: 13x13, 0.65mm pitch Samples: March 09, Production: 2H09 Applications include: IP security camera, multi-channel DVR, baby monitor, video doorbell, digital signage, personal media player, HD web cam PWM x4 Timer x6 USB 2.0HS OTG WDT EMAC 10/100 mDDR/ DDR2 EMIF NAND/ ECC EMIF MMC/ SDIO x2 10b HD/SD DAC Resizer Image Sensor Interface Histogram/3A New from DM355
H3A : AE/AWB/AF 3A Statistics OSD : Enhanced On Screen Display IPIPE (Image Pipe) DPC - defect pixel correction Noise Filter – 2D NF Advanced Color Mapping 3D-LUT DC Offset before WB Edge Enhancer False Color Suppression Re-Sizer - supports 2 different size output images Histogram LSC – Lens Shading Correction HW Face Detect Engine LDC : Lens Distortion Correction module VPSS: Video Processing Sub-System DM365 Video Processing Sub-System Image SW Tuning Tool: Targeting 2H09 Availability
6 Multi-format flexibility – The right format for your application Constrained network Increased storage H.264 Interoperability with legacy video decode MPEG-2 Mainstream MPEG-4 Simplicity MJPEG Flexibility to decode any format DM365 H.264, VC1 MPEG-4 MPEG-2
7 Flexibility to meet product requirements Multi- channel Multi- stream Multi- rate Storage Camera 1 Camera 2 DM365 Storage DM365 Internet D1 30fps CIF 30 fps 720p 30fps QCIF 15 fps Camera 1
8 Imaging flexibility with integrated Image Signal Processing (ISP) Face detection Video stabilization before after Defect pixel correction
9 Software flexibility without the complexity No royalty to TI No license fee Configurable/ not programmable Available for price adder embedded in chip cost Download from TI via click wrap license Configurable/ not programmable DM365 H.264 MPEG-4 JPEG MP3 G.711 Bundled codecs MPEG-2 VC1 WMV9 WMA AEC Additional codecs available AAC $2 $1 MPEG-2 VC1 WMV9 WMA AEC AAC $2.50 Ease-of-use codecs are black-boxed in a systems solutions approach for faster time-to-market
10 Up to 25% system cost savings EMAC Integration DM365 Saves $1.00 USB 2.0 with Phy Saves $1.00 Saves $ bit DDR2 memory interface Real-time clock Saves $0.30 Saves $1.30 Voice codec Image Signal Processing (ISP) Saves $ Video DACs Built-in ISP eliminates need for: SoC sensor or Separate ISP chip Saves > $1.00 Higher quality lens Saves > $2.00
11 Get started today! DM365 Digital Video Evaluation Module (DVEVM) –Linux board support package Drivers for UART, I2C, SPI, EDMA, NAND,MMC, SD Card, USB Host/Gadget, EMAC Video Processing Subsystem (Display, Capture, CCD Controller, Resizer, Previewer) OSS Audio (ASP), GPIO, PWM, WDTIM Uboot loader –H.264, JPEG, MPEG-4, MP3 & G.711 codecs –Video input/output, Audio in/out, UART, USB 2.0, MMC/ SDIO & JTAG –Freely available ORCADs & schematics –TMDXEVM365: $595 Order entry: March 3
DM365 Schedule Schedules –Announcement March 3, 2009 –Open Order Entry (silicon and starter kit) March 3, 2009 –DVEVM OrderMarch 3, 2009 DeliveryMay 2009 Sample Part Number: TMX320DM365AZCE EVM Part Number: TMXEVM365BET
DM365 Schedule Updates Announcement on March 3 rd Silicon: Order Entry - March 3rd with 6 – 8 week lead times Part Number TMX320DM365AZCE Preproduction quantities will be the superset device at 300MHz Targeting Qualification in September 2009 with production quantities shipping within 6 weeks Two separate speed grades will be offered in production –300MHz (1.35V supply) –270MHz Beta EVMs: Open Order Entry – March 3rd with up to 12 week lead times Part Number: TMDXEVM365BET -- will be populated with 300MHz device At launch, the first EVMs will offer a Beta LSP only. This allows the earliest possible delivery of EVMs. In the Read Me 1st card, it will direct customers to MyRegisteredSW for Beta DVSDK (with codecs) when available (see SW schedule below).
DM365 Software Schedule Beta SW: Beta DVSDK (available for download - targeting April 09) –Full DVSDK demos (Encode, Decode, Encode + Decode) –Beta Codecs (Max Performance at 300MHz) H.264 HP Limited High Profile (Progressive only, No B frames) Encode/ Universal Decode (except no interlace) –720p (1280x720) MPEG4 SP Encode/ SP Closed Loop Decode (will be universal in Release 2 of DVSDK targeted for May) –720p 30fps –SXVGA 30fps JPEG –BP Encode 66MPs / BP Decode 60MPs –Production Ready DVSDK (targeting May 09) Additional Beta Release Schedules: MPEG-4 Decoder – ASP Universal Decode –May 09 H.264 Decoder – Universal MP Decode –May 09, MPEG-2 Universal Decode –June 09 MPEG-2 Encoder (With Interlace support, No B pictures) –June 09 VC-1 MP Universal Decoder –June 09