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1 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC New prototypes for components of.

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1 1 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Lukas Püllen, Jennifer Boek, Susanne Kersten, Peter Kind, Peter Mättig, Christian Zeitnitz PIXEL 2012, Inawashiro, Japan

2 2 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Introduction Upgrade of LHC to the High-Luminosity-LHC (HL-LHC) in the years around 2020 –Increase of luminosity to L = 5·10 34 cm -2 s -1 –Targeted integrated luminosity 3000 fb -1 ATLAS inner tracker will be replaced entirely –Pixel detector (inner layers) –Strip detector (outer layers)

3 3 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Requirements of a control system for the new ATLAS pixel detector To ensure a safe operation if the ATLAS Pixel Detector the detector control system (DCS) has to meet several requirements: Radiation hard Low material cost and impact to measurements of the other ATLAS subdetectors Low power consumption (passive cooling) Easy to integrate into the ATLAS DCS framework Reliable steering of all operation relevant quantities: –Supply voltages for detector components –Switching of detector components –Temperature, voltage and current monitoring –Providing reset signals

4 4 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Idea of a control system for the new pixel detector Radiation tolerant control system for a reliable monitoring and control of the pixel detector Splitted in three paths: –safety path Hardwired interlock system –control-feedback path For all use cases –diagnostics path Detector calibration (embedded into the optical link)

5 5 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Idea of a control system for the new pixel detector The control-feedback path Star shaped network of two chips – DCS controller – DCS chip Counting room to DCS controller via CAN* DCS controller to DCS chip via I2C-HC** Data is processed locally to reduce lines Tasks of the network Measuring voltages, temperatures and humidities Delivering measured data from the detector to the user Delivering and executing user commands to the detector Distance from interaction point 100m 20m <1m *Controller Area Network **I²C-Hamming Code

6 6 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC The I2C-HC protocol Extension to the known I²C protocol by four check bits –Shortened, cyclic Hamming code (12,8) –Detects errorneous messages with two false bits –Corrects errorneous messages with one false bit Differential transmission across 20 m S8-bit data 4 check bits Ack8-bit data 4 check bits Ack Physical layer for the I2C-HC bus is inspired by CAN 2 differential lines (SDA + SCL) Dominant and recessive state Multiple nodes (4 DCS chips) on one bus Robust protocols decrease the errors in data transmission due to radiation in the DCS to less than 1 undetected error in 10 years of operation!

7 7 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Nodes of the network Concept of the DCS controller CAN node Master of the DCS chip interface Bridge between CAN and I2C-HC Multiplexer connects I2C-HC master to the corresponding I2C-HC bus (1 out of 4) Provides clock for the DCS chip Located at a service point in ATLAS (20m from the IP)

8 8 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Nodes of the network Concept of the DCS chip Radiation hard Measures environmental conditions –Temperatures (NTCs) –Voltages –Humidity (capacitive sensors) Communication interface 16 ADC channels (10 bit) 2 channels for humidity measurements 8 digital outputs –Switching parts of the detector –Distributing reset signals Low power consumption –Operational without cooling Located at the EoS card in the pixel detector (<1m from the IP)

9 9 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Existing prototypes Digital Prototypes DCS chip –Name: CoFee1 –I2C-HC slave –Chip ID –Digital outputs –Single ended data lines –TMR (Triple modular redundancy) DCS controller –Name: CoFee2 –CAN node –I2C-HC master –Bridge –Single ended data lines –2 versions: With and without TMR Analog prototypes Voltage reference –3 references in 1 chip (still under studies) –Chip contains a synthesized shift register with 1500 FF for irradiation measurements Physical layer for I2C-HC –Differential driver and receiver –Dominant and recessive state –Inspired by CAN All prototypes in 130 nm process recessive dominant recessive mV 0 V V t

10 10 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Dry runs with prototypes Testing in the lab: Tested components: –CoFee1 (DCS chip) –CoFee2 without TMR (DCS controller) –CoFee2 with TMR (DCS controller) –Physical Layer Results: –CoFee2 with TMR does not work completely Clock tree issues –Communication chain from PC to DCS chip works –Max cable length for I2C-HC ~80m at 200kHz: DCS computer Kvaser CAN DCS controller (without TMR) Physical Layer DCS chip VP230 Physical Layer

11 11 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Radiation tolerance Radiation exposure of electronics in the pixel detector up to 570 MRad Neutron equivalent dose 2·10 16 neq/cm 2 at 3000 fb -1 Expected flux of charged hadrons at the EoS card: 3·10 8 s -1 cm -2 (E>20MeV) Effects of the radiation: –Material damage due to long term irradiation –Single event effects Upsets (SEU) bitflips Latchups (SEL) shorts Transients (SET) glitches Etc Design kit issue In clocked designs handled as SEU Redundancy Triple Modular Redundancy (TMR) Each register has two clones Voter logic produces single output Voter logic

12 12 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Irradiation at PSI Proton Irradiation Facility (PIF) –Located at Paul Scherrer Institute (Switzerland) –Proton beam –Beam energy up to 99.7 MeV –Flux up to 4.25·10 9 p + s -1 cm -2 EoS: 3·10 8 s -1 cm -2 (E>20MeV) Several prototypes irradiated: –Physical Layer –CoFee1 ( DCS chip ) –CoFee2 ( DCS controller ) with TMR –CoFee2 ( DCS controller ) without TMR –Shift register (4x1500 FlipFlops) Verify reliability under irradiation Measure cross section for SEUs Test for necessity of TMR

13 13 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Irradiation of the Shift Register 4 chips on a carrier pcb with 1500 FF each Filled and read out with a pattern every 1-2 minutes Reference chip was operated in radiation free environment –Observed no bitflips Homogenious beam profile with a diameter of 2 cm Crossection (4.4 ± 0.3)·10 14 cm 2 /bit 0->1: (1.4 ± 0.2)·10 14 cm 2 /bit 1->0: (3.0 ± 0.4)·10 14 cm 2 /bit

14 14 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Irradiation of the Cofee2 without TMR Operated with beam fluxes between 5·10 8 – 4.25·10 9 cm -2 s -1 and E = 99.7 MeV Operated with commercial physical layer for differential lines Reference setup in the control room showed no errors Results: –Stable communication could not be established –Chip hang up several times and had to be resetted –Reliable operation without TMR NOT possible TMR is necessary! DCS computer Kvaser CAN II CoFee2 No TMR DCS chip VP230 Beam VP230 CoFee2 No TMR DCS chip VP230 Beam area Control room

15 15 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Irradiation of the Cofee2 with TMR Chip has clock tree issues –Only several commands work stable Operated with beam fluxes between 1·10 9 – 4.25·10 9 cm -2 s -1 and E = 99.7 MeV Overall fluence on the chip 4.97·10 13 cm -2 Operated with commercial physical layer for differential lines Results: –Writing commands work stable during irradiation –TMR corrects bitflips –Comparing measurment with the same commands in noTMR chip produced 4 errors in a fluence of 1.53·10 13 cm -2 DCS computer Kvaser CAN II CoFee2 with TMR DCS chip VP230 Beam VP230 CoFee2 with TMR DCS chip VP230 Beam area Control room

16 16 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Irradiation of the CoFee1 and the Physical Layer Operated with beam fluxes between 1·10 6 – 5·10 8 cm -2 s -1 and E = 99.7 MeV Overall fluence on the chip 4.2·10 12 cm -2 Operated with single ended lines Physical Layer chip placed behind the CoFee1 chip Results CoFee1 –5h of DCS communication were entirely faultless –TMR cleaned out all errors Results Physical Layer –No change in transition times and signal delay within the errors of the measurements of the scope

17 17 of 17 LUKAS PÜLLEN New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC Summary and Outlook We aim for a reliable control system for ATLAS pixel –Radiation tolerant –Network topology –Reliable busses –Measure voltages, temperatures and humidity –Switch detector components –Provide reset signals 3 digital prototypes –Working DCS chip –DCS controller with issues (understood) 2 Analog prototypes –Working physical layer –Voltage references Study voltage references Further study the results of the irradiation at PSI –Power consumption Next Chip in development: ADC parts –DAC + comparator –Successive approx logic Next submission: Corrected DCS controller design


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