2 Workshop Objectives By the end of this class, you will … Understand the function and application of Digital Clock Managers (DCMs)Unlock a few mysteries on how DCMs operateMore mysteries revealed in Part IIBecome a Clock Wizard and easily configure a DCMHave a few new approaches to teach customers on DCMsLegitimately say “DCMs Don’t Confuse Me”
3 Up the Learning Curve e s i t r e p x E Real-World Experience Part II This class assumes that you have at least a passing familiarity with the Digital Clock Managers (DCMs) within Xilinx FPGAs.This is Part 1 of a two part class. Part 1 is designed to introduce you to basic DCM concepts and capabilities. If you’re already an advanced DCM user, I think that you’ll learn a few new techniques that you can use to teach customers and other FAEs.Part 2 extends the concepts of Part 1 and covers a few advanced areas.After attending both sessions, you should have a good work knowledge of the DCM. However, only real-world design experience will make you an expert.What’s a DCM?Time
4 DCMs Everywhere!In this presentation, the Spartan-3 DCM demonstrates basic principals and conceptsThe Spartan-3 DCM is similar to Virtex-II and Virtex-II ProThe DLL in the DCM is similar to the DLL in Virtex/E and Spartan-II/EVirtex-4 DCM also employees similar conceptsAnd now a message from our sponsors …Spartan-3 DCMs are used in this class to demonstrate various concepts.The Spartan-3 DCM is nearly identical to that found on Virtex-II and Virtex-II Pro FPGAs, minus a few issues.The Delay Locked Loop (DLL) within each DCM is similar to the DLL found in Virtex, Virtex-E, Spartan-II, and Spartan-IIE FPGAs.Virtex-4 employees all the latest generation capabilities. However, the concepts described in this class also apply to Virtex-II.
5 DCMs: The Clock Problem Solver Eliminate clock skew—improved performance!Multiply or divide an incoming clock or create a completely new clock frequencyPhase shift a clockCondition a clock input to create 50% duty cycleAny or all of the above, simultaneously!QUESTION TO THE CLASS: What are a few of the clocking problems that you face in system design?PROMPTS: Ever wish that you had faster clock-to-output time? How do you obtain that?Ever wish that you could create another clock frequency?DCMs have a variety of system applications. DCMs help eliminate clock skew either within the FPGA or within the system, improving overall performance.Now some FAEs think that DCMs are there to help generate customer calls.One key message: Not every application requires a DCM. If you don’t need it, don’t use it. Unless required, DCMs are just a needless complexity. Don’t need it? Then don’t use it!
6 DCM, Where Are You?XC3S50 onlyLocated at top and bottom of block RAM/multiplier column(s)Four DCMs in each Spartan-3, except XC3S50, which has two DCMDCMs have direct connections to global buffers along the same edgeEach DCM has a unique location stringWatch PAR placement!Global buffer multiplexersDCM_X1Y1DCM_X1Y0DCM_X0Y0DCM_X0Y1Block RAMColumnEmbeddedMultiplierColumnGlobal buffer multiplexers
7 Delay-Locked Loop (DLL) DCM Block DiagramDigital FrequencySynthesizerPhase Shifter (PS)Input StageOutput StageDelay TapsStatus LogicDelay-Locked Loop (DLL)DCMCLK0CLKINCLK90CLK180CLK270Up to all nine clock outputs available simultaneouslyCLKFBCLK2XCLK2X180CLKDVAny four of nine clock outputs optionally connect to global buffers along same edgeCLKFXCLKFX180PSENPSINCDECPSDONEPSCLKSTATUS[7:0]RSTLOCKED
10 In the Real World, You’re Skewed FPGABOtherCADbDevice onBoardDcADbDcTwo different timing relationships!
11 No Skew, No Problem Symbol -4 TIOCKP 1.72 ns Q CLK CLK Q Flip-flop DelaySymbol-4TIOCKP1.72 ns
12 Skew: The Time Thief Symbol -4 TIOCKP 1.72 ns TICKOF 4.56 ns Q CLK CLK Flip-flopQInput BufferClock Distribution
13 Quick Review: What We Want FPGAABCOtherDevice onBoard
14 How Do We Get There? What if we provide advance clocks? Other BOtherACDevice onBoardWhat if we provide advance clocks?
15 The Answer? Clairvoyant Logic, Of Course! B-Db+ Db = NO SKEW!OtherDbcACDevice onBoardADbBDcC
16 Houston, We Have a Problem First Rule of Time Travel: You can’t go backwards!Clairvoyant logic does not exist (well, at least not yet)Now what!?!
17 Forward Thinking Other Device on Board B A C Clock Period (T) A Delay=T - DbBbDcDelay=T- DcC
18 ? You Don’t! The Tough Questions How do you specify the clock period? How do you determine the delays for Db and Dc?How do you voltage- and temperature-compensate the design?You Don’t!?
19 Classroom Experiments Everyone please take out your Delay-Lock Loop (DLL) simulatorsLAB 1: Feedback, frequency and phase lockingLAB 2: Stable, monotonic clock
20 The Magical Delay-Locked Loop (DLL) ADJUSTToo EarlyClockFeedbackEach of the 256 taps is between 30 to 60 psDelay LineClockDelay matched Clock and Feedback path lengthsPhaseDetectorFeedback
21 The Magical Delay-Locked Loop (DLL) Perfect!ClockLOCKEDFeedbackDelay LineClockPhaseDetectorFeedbackDelay tap settings updated periodically for temperature/voltage compensationUpdate rate controlled by an internal attribute called FACTORY_JF
22 Resulting TimingSymbolDescription-4TIOCKPOutput flip-flop clock-to-output1.72 nsTICKOFPin-to-pin clock-to-output delay, no DCM4.56 nsTICKOFDCMPin-to-pin clock-to-output delay, with DCM deskew1.52 ns~ 3 ns eliminated from clock distribution delay when using internal feedback!Output delay nearly completely eliminated when using external feedback
23 Locking The DLL requires a stable monotonic clock input Stable clock frequencyMinimal jitterThe DCM LOCKED output indicates when the DCM has acquired and locked to the incoming clockApplication should ignore the DCM clock outputs until LOCKED assertedNo clock edges can be missing during the locking processIf clock is not yet stable, hold the DCM in resetExternal enabled oscillatorsExternal frequency scalingCascaded DCMs
25 LOCKED and STATUS Bits LOCKED (Output clocks good) The DCM clock outputs are not valid until LOCKED=1If LOCKED 0, reset the DCM (hit delay tap limits)It is possible for LOCKED=1 but the output clocks are invalidSTATUS bits provide additional detailSTATUS – CLKIN StoppedSTATUS=1 if CLKIN stops toggling, reset the DCMSTATUS – CLKFX, CLKFX180 StoppedSTATUS=1 if CLKFX or CLKFX180 outputs stop, and these outputs are used in the design, reset the DCM
26 Feedback from a Reliable Source DLL requires feedback from one of two DCM outputsCLK0 (1X feedback)CLK2X (2X feedback)CLK2X not presently available on all devicesPresently supported only on XC3S50 and XC3S1000Coming to the remainder of the family in 2005Not supported in Virtex-II Pro
27 DCMs Integrate into FPGA Clock Path IBUFGBUFGPADCLKINCLKFBCLKxDCMIBUFGBUFGPAD
28 Internal Feedback IBUFG BUFG DCM (or BUFGMUX, or BUFGCE) Clock to I O CLKINCLK0internal(or CLK2X)FPGA logic(alternate clock inputsDCMpossible, but not fullyskew adjusted)CLKFBLOCKED(Internal Feedback)
32 DCM Rules and Lots of Them The DLL outputs operate up to 280 MHz unless you use phase shifting, then the maximum frequency is 165 MHzThe DFS accepts input clock frequencies down to 1 MHz if you are not using the Delay-Locked Loop (DLL)The CLKDV output can only divide the incoming clock by certain valuesThe variable phase shifter uses the PSEN, PSINCDEC, PSCLK, PSDONE, and STATUS bitsThe DLL requires that the CLKFB input be connected. The DFS does not require feedbackAny four of the nine possible DCM outputs can connect to global clock buffersThe CLK90 and CLK270 outputs are only available when the DLL is in low-frequency modeThe output jitter on the CLKFX and CLKFX180 output depends on the DFS Multiply and Divide settingsThe amount of phase shift may be limited due to the incoming clock frequencyThe frequencies supported by the DFS may be limited by the DLL if used within the same DCMThe minimum DLL output frequency must be 24 MHz or greaterThe DLL feedback must come from either CLK0 or CLK2X. The CLK2X feedback does not work for all devices
33 DCM Rule #1 All DCMs in a design must be instantiated CLKINCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDVCLKFXCLKFX180STATUS[7:0]LOCKEDPSDONECLKFBRSTPSENPSINCDECPSCLKDCMDSSENAll DCMs in a design must be instantiatedLanguage Templates available in ISEClock Wizard makes it easy
35 ISE 6.3i Clock Wizard Greatly simplifies using a DCM! Graphically configure aDigital Clock Manager(DCM)Vendor-specificVHDL or VerilogVHDL or VeriloginstatiationtemplateXilinx ArchitectureWizard (XAW)settings fileUser constraintsfile (UCF)Greatly simplifies using a DCM!
36 Two Methods to Invoke Clock Wizard From Window Start menuStart Xilinx ISE 6 Accessories Architecture WizardFrom within Project NavigatorProject New Source
45 What is Jitter? Uncertainty on exact timing of a clock edge Ideal ClockMeasured clock periodNumberofsaplPeak-to-peak Period JitterUncertainty on exact timing of a clock edgeAffected by power noise, decoupling, SSOs, internal switching, etc.Period (peak-to-peak) jitter specification is most quotedSpecified as either absolute (300 ps) or deviation (± 150 ps)
46 Clock Jitter Specifications Period (peak-to-peak) jitterCycle-to-cycle jitterUnit Interval (UI)TT1=T+100 psT2=T1-150 psExampleUI=0.10 means that period jitter is 10% of the total bit periodPeak-to-peakPeriod JitterBit PeriodPeak-to-peak period jitter,represented as fraction ofUnit IntervalUnit Interval (UI)
47 Jitter Effects on Cycle Timing Single Data Rate (SDR)EarliestArrivalAvailable PeriodHalfPeriod JitterClock PeriodBit Period
48 Jitter Effects on Cycle Timing Double Data Rate (DDR)EarliestArrivalConsider both clock edges in DDR applicationsAvailablePeriodAvailablePeriodJitterBit PeriodNo duty-cycle distortioneffects consideredClock Period
49 Jitter Effects on Flip-Flop Timing Early Clock EdgeLate Clock EdgeHalfPeriod JitterHalfPeriod JitterIncreases input set-up timeReduces minimum clock-to-output timeIncreases hold timeIncreases maximum clock-to-output time
50 Minimizing Clock Jitter Switching noise causes jitterProper power, PCB design, and decouplingXAPP623: Power System Distribution GuidelinesPCB Checklist% CLB switching contributes noiseObey SSO recommendations (in Spartan-3 data sheet)VCCAUX is voltage source for DCMsGND pins for logic and DCMs are commonJitter on input clockGarbage in, garbage outTake care of your clocks and your clocks will take care of you
51 GOVERNMENT HEALTH WARNING: FAILING TO APPLY XAPP623 COULD BEHAZARDOUS TO YOUR DCM DESIGN ANDYOUR MENTAL HEALTH
52 XAPP462: The DCM Reference A comprehensive 68-page “tree killer”Updated for ISE 6.3i and latest Spartan-3 DCM knowledge
53 Second Verse, Same as the First* If you enjoyed this session, please also attend …Secrets of the DCMPart II* Only a little bit louder and a whole lot worse