Secrets of the DCM (Part I) 2 Workshop Objectives Understand the function and application of Digital Clock Managers (DCMs) Unlock a few mysteries on how DCMs operate – More mysteries revealed in Part II Become a Clock Wizard and easily configure a DCM Have a few new approaches to teach customers on DCMs Legitimately say DCMs D ont C onfuse M e By the end of this class, you will …
Secrets of the DCM (Part I) 3 Real-World Experience Up the Learning Curve Whats a DCM? Time E x p e r t i s e Part I Part II
Secrets of the DCM (Part I) 4 DCMs Everywhere! In this presentation, the Spartan-3 DCM demonstrates basic principals and concepts The Spartan-3 DCM is similar to Virtex-II and Virtex-II Pro The DLL in the DCM is similar to the DLL in Virtex/E and Spartan-II/E Virtex-4 DCM also employees similar concepts
Secrets of the DCM (Part I) 5 DCMs: The Clock Problem Solver Eliminate clock skewimproved performance! Multiply or divide an incoming clock or create a completely new clock frequency Phase shift a clock Condition a clock input to create 50% duty cycle Any or all of the above, simultaneously! Dont need it? Then dont use it!
Secrets of the DCM (Part I) 6 DCM, Where Are You? Block RAM Column DCM_X1Y1 DCM_X1Y0 DCM_X0Y0 DCM_X0Y1 Global buffer multiplexers Embedded Multiplier Column Global buffer multiplexers XC3S50 only Located at top and bottom of block RAM/multiplier column(s) Four DCMs in each Spartan- 3, except XC3S50, which has two DCM DCMs have direct connections to global buffers along the same edge Each DCM has a unique location string – Watch PAR placement!
Secrets of the DCM (Part I) 7 DCM DCM Block Diagram Digital Frequency Synthesizer Phase Shifter (PS) Input Stage Output Stage Delay Taps Status Logic Delay-Locked Loop (DLL) PSINCDEC PSEN PSCLK CLKIN CLKFB RST PSDONE STATUS[7:0] LOCKED CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 Up to all nine clock outputs available simultaneously Any four of nine clock outputs optionally connect to global buffers along same edge
Lesson One Avoid being skewed!
Secrets of the DCM (Part I) 9 The Ideal World Other Device on Board FPGA A B C A B C SKEW
Secrets of the DCM (Part I) 10 In the Real World, Youre Skewed Other Device on Board A FPGA A B B C C c b c b Two different timing relationships!
Secrets of the DCM (Part I) 11 No Skew, No Problem Symbol-4 T IOCKP 1.72 ns Q CLK Q Flip-flop Delay
Secrets of the DCM (Part I) 12 Skew: The Time Thief CLK Q Input Buffer Clock Distribution Flip-flop Symbol-4 T IOCKP 1.72 ns T ICKOF 4.56 ns Q CLK
Secrets of the DCM (Part I) 13 Quick Review: What We Want Other Device on Board FPGA A B C A B C
Secrets of the DCM (Part I) 14 How Do We Get There? Other Device on Board A B C What if we provide advance clocks?
Secrets of the DCM (Part I) 15 A B C b c The Answer? Clairvoyant Logic, Of Course! Other Device on Board A B C b c - b + b = NO SKEW!
Secrets of the DCM (Part I) 16 Houston, We Have a Problem First Rule of Time Travel: You cant go backwards! Clairvoyant logic does not exist (well, at least not yet) Now what!?!
Secrets of the DCM (Part I) 17 Forward Thinking Other Device on Board A B C A B C b c Delay=T- c Delay=T - b Clock Period (T)
Secrets of the DCM (Part I) 18 The Tough Questions How do you specify the clock period? How do you determine the delays for b and c? How do you voltage- and temperature- compensate the design? You Dont! ?
Secrets of the DCM (Part I) 19 Classroom Experiments Everyone please take out your Delay-Lock Loop (DLL) simulators LAB 1: Feedback, frequency and phase locking LAB 2: Stable, monotonic clock
Secrets of the DCM (Part I) 20 The Magical Delay-Locked Loop (DLL) Delay Line Clock Feedback Clock Feedback Too Early Each of the 256 taps is between 30 to 60 ps Phase Detector ADJUST Delay matched Clock and Feedback path lengths
Secrets of the DCM (Part I) 21 The Magical Delay-Locked Loop (DLL) Phase Detector Delay Line Clock Feedback Clock Feedback Perfect! Delay tap settings updated periodically for temperature/voltage compensation Update rate controlled by an internal attribute called FACTORY_JF LOCKED
Secrets of the DCM (Part I) 22 Resulting Timing SymbolDescription-4 T IOCKP Output flip-flop clock-to-output 1.72 ns T ICKOF Pin-to-pin clock-to-output delay, no DCM 4.56 ns T ICKOFDCM Pin-to-pin clock-to-output delay, with DCM deskew 1.52 ns ~ 3 ns eliminated from clock distribution delay when using internal feedback! Output delay nearly completely eliminated when using external feedback
Secrets of the DCM (Part I) 23 Locking The DLL requires a stable monotonic clock input – Stable clock frequency – Minimal jitter The DCM LOCKED output indicates when the DCM has acquired and locked to the incoming clock – Application should ignore the DCM clock outputs until LOCKED asserted No clock edges can be missing during the locking process If clock is not yet stable, hold the DCM in reset – External enabled oscillators – External frequency scaling – Cascaded DCMs
Secrets of the DCM (Part I) 24 Locking Process
Secrets of the DCM (Part I) 25 LOCKED and STATUS Bits LOCKED (Output clocks good) – The DCM clock outputs are not valid until LOCKED=1 – If LOCKED 0, reset the DCM (hit delay tap limits) – It is possible for LOCKED=1 but the output clocks are invalid – STATUS bits provide additional detail STATUS – CLKIN Stopped – STATUS=1 if CLKIN stops toggling, reset the DCM STATUS – CLKFX, CLKFX180 Stopped – STATUS=1 if CLKFX or CLKFX180 outputs stop, and these outputs are used in the design, reset the DCM
Secrets of the DCM (Part I) 26 Feedback from a Reliable Source DLL requires feedback from one of two DCM outputs – CLK0 (1X feedback) – CLK2X (2X feedback) CLK2X not presently available on all devices – Presently supported only on XC3S50 and XC3S1000 – Coming to the remainder of the family in 2005 – Not supported in Virtex-II Pro
Secrets of the DCM (Part I) 27 DCMs Integrate into FPGA Clock Path IBUFGBUFG PAD IBUFGBUFG PAD CLKIN CLKFB CLKx DCM
Secrets of the DCM (Part I) 28 Internal Feedback IO BUFG Clock to internal FPGA logic (or BUFGMUX, or BUFGCE) (Internal Feedback) (alternate clock inputs possible, but not fully skew adjusted) IO IBUFG CLKINCLK0 CLKFBLOCKED DCM (or CLK2X)
Secrets of the DCM (Part I) 29 External Feedback CLKINCLK0 CLKFBLOCKED DCM (or CLK2X) IO OBUF IO FPGA Other Device(s) on Board CLK ENABLE (External Feedback Trace) Circuit-board trace delay, additional clock buffers, etc. RESETD WCLK A[3:0] Q INIT=000F SRL16 IO IBUFG IO Delay matched Clock and Feedback path lengths
Secrets of the DCM (Part I) 30 Clock Wizard Makes it Easy!
Lesson Two Wizard School
Secrets of the DCM (Part I) 32 DCM Rules and Lots of Them The DFS accepts input clock frequencies down to 1 MHz if you are not using the Delay-Locked Loop (DLL) The DLL outputs operate up to 280 MHz unless you use phase shifting, then the maximum frequency is 165 MHz The CLK90 and CLK270 outputs are only available when the DLL is in low-frequency mode The minimum DLL output frequency must be 24 MHz or greater The DLL feedback must come from either CLK0 or CLK2X. The CLK2X feedback does not work for all devices The variable phase shifter uses the PSEN, PSINCDEC, PSCLK, PSDONE, and STATUS bits The output jitter on the CLKFX and CLKFX180 output depends on the DFS Multiply and Divide settings Any four of the nine possible DCM outputs can connect to global clock buffers The CLKDV output can only divide the incoming clock by certain values The frequencies supported by the DFS may be limited by the DLL if used within the same DCM The DLL requires that the CLKFB input be connected. The DFS does not require feedback The amount of phase shift may be limited due to the incoming clock frequency
Secrets of the DCM (Part I) 33 DCM Rule #1 All DCMs in a design must be instantiated Language Templates available in ISE Clock Wizard makes it easy CLKINCLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 STATUS[7:0] LOCKED PSDONE CLKFB RST PSEN PSINCDEC PSCLK DCM DSSEN
Secrets of the DCM (Part I) 35 ISE 6.3i Clock Wizard Clock Wizard Graphically configure a Digital Clock Manager (DCM) Vendor-specific VHDL or Verilog instatiation template Xilinx Architecture Wizard (XAW) settings file User constraints file (UCF) Greatly simplifies using a DCM!
Secrets of the DCM (Part I) 36 Two Methods to Invoke Clock Wizard From Window Start menu – Start Xilinx ISE 6 Accessories Architecture Wizard From within Project Navigator – Project New Source
Secrets of the DCM (Part I) 37 Project Navigator Method
Secrets of the DCM (Part I) 38 Selecting the Right Wizard
Secrets of the DCM (Part I) 39 General Setup
Secrets of the DCM (Part I) 40 Assigning Global Buffers BUFG I0O BUFGCE I0O CE O S BUFGMUX I0 I1 I0 Global Buffer Enabled Buffer Clock Mux Local Routing Lowskewline
Secrets of the DCM (Part I) 41 Frequency Synthesizer (back on General Setup)
Secrets of the DCM (Part I) 42 Voila!
Secrets of the DCM (Part I) 43 Instantiation Template Available for both VHDL and Verilog VHDL Example
Lesson Three Jitter
Secrets of the DCM (Part I) 45 What is Jitter? Uncertainty on exact timing of a clock edge Affected by power noise, decoupling, SSOs, internal switching, etc. Period (peak-to-peak) jitter specification is most quoted – Specified as either absolute ( 300 ps ) or deviation ( ± 150 ps ) Ideal Clock Measured clock period N u m b e r o f s a m p l e s Peak-to-peak Period Jitter
Secrets of the DCM (Part I) 46 Clock Jitter Specifications Period (peak-to-peak) jitter Cycle-to-cycle jitter Unit Interval (UI) T 1 =T ps T 2 =T ps T 0 Bit Period Peak-to-peak Period Jitter Unit Interval (UI) Peak-to-peak period jitter, represented as fraction of Unit Interval Example UI=0.10 means that period jitter is 10% of the total bit period
Secrets of the DCM (Part I) 47 Half Period Jitter Jitter Effects on Cycle Timing Bit Period Single Data Rate (SDR) Available Period Earliest Arrival Clock Period
Secrets of the DCM (Part I) 48 Jitter Effects on Cycle Timing Double Data Rate (DDR) Clock Period No duty-cycle distortion effects considered Earliest Arrival Bit Period Consider both clock edges in DDR applications Available Period Jitter Available Period
Secrets of the DCM (Part I) 49 Jitter Effects on Flip-Flop Timing Early Clock EdgeLate Clock Edge Increases input set-up time Reduces minimum clock-to- output time Increases hold time Increases maximum clock-to- output time Half Period Jitter Half Period Jitter
Secrets of the DCM (Part I) 50 Minimizing Clock Jitter Switching noise causes jitter – Proper power, PCB design, and decoupling XAPP623: Power System Distribution Guidelines PCB Checklist – % CLB switching contributes noise – Obey SSO recommendations (in Spartan-3 data sheet) VCCAUX is voltage source for DCMs GND pins for logic and DCMs are common Jitter on input clock – Garbage in, garbage out Take care of your clocks and your clocks will take care of you
Secrets of the DCM (Part I) 51 GOVERNMENT HEALTH WARNING: FAILING TO APPLY XAPP623 COULD BE HAZARDOUS TO YOUR DCM DESIGN AND YOUR MENTAL HEALTH
Secrets of the DCM (Part I) 52 XAPP462: The DCM Reference A comprehensive 68- page tree killer Updated for ISE 6.3i and latest Spartan-3 DCM knowledge
Secrets of the DCM (Part I) 53 Second Verse, Same as the First* If you enjoyed this session, please also attend … * Only a little bit louder and a whole lot worse Secrets of the DCM Part II
Secrets of the DCM (Part I) 54 Questions?
Secrets of the DCM (Part I) 55 Please Fill Out and Return the Feedback Forms! Steve Knapp Secrets of the DCM: Part 1 Forms are in the back of your FAE conference book Please return at back of the room Thank You!
Secrets of the DCM (Part I) 56 Jump Point Return to last slide viewed Overview Lesson 1: Avoid Being Skewed Lesson 2: Clock Wizard School Lesson 3: Clock Jitter Session Evaluation Forms