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Secrets of the DCM: Part 2

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1 Secrets of the DCM: Part 2
Steven Knapp General Products Division NOTICE: This is an early draft of this presentation. Please visit the Xilinx Sales Partner Web (SPW) for the latest version. © 2004 by Xilinx, Inc. All rights reserved. (v1.2, 11-OCT-2004)

2 Continuing On … This is a continuation of Secrets of the DCM: Part 1 that covered the following topics … Overview of the DCM and its applications Basic Delay Locked-Loop (DLL) operation Clock Wizard Clock Jitter

3 Workshop Objectives By the end of this class, you will …
Understand how the DCM can phase shift clocks Understand how to generate other clock frequencies Learn how to build high-speed data interfaces Overcome various DCM limitations Legitimately say “DCMs Don’t Confuse Me”

4 Lesson Four Phase Shifting

5 Delay-Locked Loop (DLL)
DCM Block Diagram DCM Digital Frequency Synthesizer Phase Shifter (PS) Input Stage Output Stage Delay Taps Status Logic Delay-Locked Loop (DLL) CLK0 CLKIN CLK90 CLK180 CLK270 CLKFB CLK2X CLK2X180 CLKDV CLKFX CLKFX180 PSEN PSINCDEC PSDONE PSCLK STATUS[7:0] RST LOCKED

6 Phase Shifting The DCM provides various phase shifting options
Dedicated phase shift outputs These signals always maintain their relationship Quadrant: CLK0, CLK90, CLK180, CLK270 Half-Period: CLK2X/CLK2X180, CLKFX/CLKFX180 Fixed or Variable phase shifting Adjust the phase relationship of all DCM clock outputs Requires the DCM’s DLL function

7 Quadrant Phase Shifts Delay (fraction of T 180 CLK180 270 T CLK270 90 ¼T CLK90 1T clock period) Phase Shift (degrees) 360 CLK0 Clock Period (T) CLK90 and CLK270 only available in low-frequency mode

8 Half-Period Phase Shift
Delay (fraction of T 1T clock period) Phase Shift (degrees) 180 360 CLK2X/CLK2X180 and CLKFX/CLKFX180 are similar CLK0 CLK180 Clock Period (T) Highly useful for high-performance Dual-Data Rate (DDR) applications Guarantees precise half-period timing

9 Precise Timing with Half-Period Phase Shifting
DDR Example “Local inversion” Precise Timing with Half-Period Phase Shifting “Complementary” Clock Inversion at I/O Block Introduces Duty-cycle Distortion < 150 MHz ≥ 150 MHz

10 Review: The DLL Negative Phase Shift Positive Phase Shift Clock Feedback Delay Line Clock Phase Detector Feedback DLL shifts the feedback until the Clock and the Feedback are in phase (0° phase shift) DLL controls the phase relationship, can be other than 0°

11 Fixed Phase Shifting CLKIN Fixed Phase Shift + Limit – Limit The PHASE_SHIFT attribute determines the initial phase shift position. DCM initially asserts LOCKED with this phase shift value. DCM returns to this value upon RESET. Clock Outputs FIXED Choose Clock Wizard Phase Shift Type: NONE Value: 23 Enter the Fixed phase shift value 2.695 ns Degrees Resulting fixed phase shift in nanoseconds and degrees of phase shift Fixed phase shift value set during configuration, unchangeable Affects all DCM clock outputs

12 Checking If You’re Awake
A DCM has a FIXED phase shift of 10° What is the phase relationship between CLK0 and CLK90? What is the phase relationship between CLKIN and CLK0? What is the phase relationship between CLKIN and CLK90? Always 90° 10° = 0°+ 10° 100° = 90°+ 10°

13 Delay Line and Frequency
LIMIT Clock Delay Line Clock Phase Detector Feedback Delay line has 255 taps, each 30 ps to 60 ps Maximum guaranteed delay line is 10 ns, ~40 ps per tap Clock inputs above 100 MHz can be shifted a full period (360°) Shift resolution defined by individual tap delay

14 Shift Limits < 100 MHz BEYOND LIMIT Clock Delay Line Clock Phase Detector Feedback Clock inputs < 100 MHz have clock period longer than the guaranteed tap length (> 10 ns) Can only shift the clock a fraction of the clock period (<360°)

15 Phase-Shift Limits FINE_SHIFT_RANGE = Guaranteed length of delay line = 10 ns (per data sheet) TCLKIN = Period of CLKIN input clock TCLKIN > FINE_SHIFT_RANGE (Frequency < 100 MHz) TCLKIN ≤ FINE_SHIFT_RANGE (Frequency > 100 MHz)

16 Variable Phase Shifting
CLKIN The PHASE_SHIFT attribute determines the initial phase shift position. DCM initially asserts LOCKED with this phase shift value. DCM returns to this value Clock Outputs upon RESET. Dynamic Phase Shift - Limit + Limit Fixed Phase Shift Fixed Phase Shift + Limit + Limit Increment Phase Shift Value Decrement Phase After the DCM asserts LOCKED, the FPGA application can increment or decrement the present phase shift value using the Dynamic Phase Shift Control logic. PSEN PSINCDEC PSCLK PSDONE STATUS[0] Enable Increment/Decrement Phase Shift Clock Phase Shift Done Variable Phase Shift Overflow DCM Variable Phase Shift Control

17 Variable Phase Shift Timing
LOCKED remains asserted during a variable phase shift operation

18 Phase Shift Mathematics
Convert Negative Phase Shift to Positive Phase Shift Alternate Phase Shift Solutions Convert Phase Shift in Degrees to Phase Shift in Nanoseconds

19 Lesson Five Clock Synthesis

20 Frequency Synthesis Clock Multiplication Clock Division
DCM F n -bits wide High-speed serial data down-converted to slower parallel data Clock Division DCM F Ÿ m -bits wide Slower parallel data up-converted to high- speed serial data Clock Multiplication FPGA F Overclocked, time-shared logic DCM Ÿ x Clock Synthesis Low cost design technique: Utilize full performance of the FPGA

21 Frequency Synthesis Output clocks are phase aligned
when using clock feedback via the CLKFB input. De-skewed Clock CLKIN CLK0 F=F CLKIN 50% duty cycle when DCM DUTY_CYCLE_CORRECTION=TRUE CLKFB CLK2X CLK2X180 F=2 Ÿ F CLKIN Clock Doubler 50% duty cycle Output available only when DLL_FREQUENCY_MODE=LOW CLKDV Clock Divider F= F CLKIN CLKDV_DIVIDE Usually 50% duty cycle, depending on conditions CLKFX CLKFX180 Frequency Synthesizer F= F CLKIN Ÿ CLKFX_MULTIPLY CLKFX_DIVIDE 50% duty cycle Does not require CLKFB input

22 Clock Synthesis Options
Function DCM Output(s) Frequency Functional Unit Feedback Required? Clock Doubler CLK2X CLK2X180 2*FCLKIN DLL Yes Clock Divider CLKDV FCLKIN/DIV Frequency Synthesizer CLKFX CLKFX180 FCLKIN *M/D DFS Optional

23 Clock Divider CLKDV output requires the DLL and consequently the CLKFB feedback For Spartan-3, the CLKDV_DIVIDE attribute can be … 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, 16 Lower output jitter when CLKDV_DIVIDE is an integer 50% duty-cycle output usually Except when operating in High Frequency mode and CLKDV_DIVIDE is a non-integer (i.e., 1.5)

24 Digital Frequency Synthesizer (DFS)
CLKFX/180 output frequency controlled by fraction of two attributes CLKFX_MULTIPLY = {2,3,4• • •32} CLKFX_DIVIDE = {1,2,3,4• • •32} Reduce to least common multiple CLKIN and CLKFX/180 outputs are more limited when also using the DLL Using the DLL with the DFS limits the frequency range When used, DDL and DFS are phase aligned every CLKFX_DIVIDE cycles of CLKIN CLKFX_MULTIPLY cycles of CLKFX (from General Setup window)

25 Period Jitter on CLKFX Maximum period jitter for CLKFX output is characterized Depends on multiply and divide values Depends on input and output frequencies Room temperature (25°C) Nominal voltages 50% CLBs and 40 simultaneous outputs switching at 100 MHz Jitter reported by Clock Wizard Spartan-3 jitter is effectively same as Virtex-II Pro

26 Spartan-3 CLKFX Jitter Equations
CLKFX/CLKFX180 Output Frequency Peak-to-peak Period Jitter (Unit Interval) B = 0.05 when FCLKIN > 8 MHz, else = 0.04 K = CLKFX_MULTIPLY when CLKFX_MULTIPLY > CLKFX_DIVIDE, else = CLKFX_DIVIDE Peak-to-peak Period Jitter (ns)

27 Jitter on CLKFX (from General Setup window)

28 Cascading DCMs DCMs can be cascaded, but there is no dedicated routing available for this The specified output jitter from the first DCM must not exceed the specified input jitter of the second DCM CLKFX output practically eliminated for the first DCM stage due to jitter Keep second DCM reset until first DCM locks WARNING: CLKDV does not toggle until LOCKED1 Requires three flip-flops to synchronize reset Function also available in the DCM Wizard

29 Clock Wizard Cascade DCMs

30 System vs. Source Synchronous Design
Lesson Six System vs. Source Synchronous Design

31 System Synchronous Assumes a single, system-wide clock
DLL path includes delay to compensate for clock path Ensures no hold time requirement at the receiver System synchronous is the default assumption

32 Source Synchronous Clock generated by same source as data
Typically, clock and data have same phase No compensation for clock path delay Receiver hold time is not an issue Clock MUST be phase shifted in the receiver

33 System vs. Source Synchronous Timing
+ Fixed or Dynamic Phase Shift Data capture window or data “eye” DATA_IN SYSTEM_SYNCHRONOUS SOURCE_SYNCHRONOUS A little extra delay guarantees no hold time requirement Application phase shifts clock to middle of data eye

34 Deskew Adjustment in Clock Wizard
(from General Setup window)

35 Lesson Seven Optional Divide by 2

36 Dividing Input Clock by 2
Optional divide-by-2 function on CLKIN input Dedicated high-speed toggle flip-flop inside the DCM Divide down a high-frequency clock to the range acceptable to the DCM Clean up a non-50% duty-cycle input to guarantee a clean 50% clock input 50% to 60% duty-cycle improves DLL performance Low/high duty cycles will stop the DCM working See data sheet for specs

37 Divide-by-2 in Clock Wizard
(from General Setup window)

38 622 Mbps Interface: Pulling it all together
Lesson Eight 622 Mbps Interface: Pulling it all together

39 Spartan-3 DCM Errata CLK2X feedback
Fixed on XC3S50 and XC3S1000 Coming on remainder of Spartan-3 family in 2005 Negative phase shift (No longer an issue) Maximum DLL frequency in High Frequency mode

40 Problem Statement We want to build a LVDS transmitter operating at 622 Mbps with a 311 MHz input clock Issues: Probably NONE DCM not required as long as the input clock has roughly 50% duty cycle Transmitter macros with embedded FIFO are available for the Spartan-3 in 4:1, 6:1, 7:1 and 8:1 SERDES factors Transmitter macros are also available without the FIFO for designs that use the DCM

41 622Mbit/second DDR Transmitter Example
FPGA FDDRCPE OBUFDS D0 Q 311 MHz D1 No resistors required for differential transmitters. IBUFGDS_DIFF_OUT 100 W BUFG CE C0 311 MHz C1 BUFG Clock output shown – data outputs are similar

42 MISSION IMPOSSIBLE? Problem Statement
We want to build a LVDS receiver operating at 622 Mbps with a 311 MHz input clock Issues: We have and need a 311 MHz clock We need phase shifting, which requires the DLL It is a DDR application Worry about jitter and duty-cycle distortion MISSION IMPOSSIBLE?

43 Typical 622 Mbps DDR DCM Configuration
DDR interface uses half-rate clock 311 MHz CLK0 311 MHz CLKFB CLKIN CLK180 Exceeds DLL maximum frequency Phase shift control Exceeds DLL maximum phase shift frequency of 165 MHz

44 Fundamental Problem 311 MHz forwarded clock coming right at us!
Spartan-3 DCM supports shifting if CLKIN ≤ 165 MHz What to do? Use the dedicated divide by 2 option at the input of the DCM Clock applied to the DLL in the DCM will be MHz Guarantees 50% duty-cycle  DCM Friendly! Phase shifting is performed with DCM in low-frequency mode Use the 2X and 2X180 DCM outputs to reproduce to the required 311 MHz once phase shift has been applied

45 Example 622 Mbps DDR DCM Configuration
DDR interface uses half-rate clock 311 MHz CLK2X 311 MHz CLKFB CLKIN CLK2X180 Clock double reproduces original input frequency Phase shift control Because input clock is 311 MHz and further reduced with optional divide-by-2, DCM support phase shifting CLKIN_DIVIDE_BY_2=TRUE Reduces 311 MHz incoming clock to <165 MHz, placing DCM in low-frequency mode CLK2X output supports up to 330 MHz! NOTE: Double jitter as well Some devices require additional BUFG due to CLK2X feedback errata

CLK0 feedback required for specific Phase shifter operates part numbers. Optionally, use at up to 165 MHz. general-purpose interconnect but phase alignment not guaranteed. 155.5 MHz 100 W IBUFGDS DCM BUFG 311 MHz CLKIN CLK0 CLKFB BUFG The CLKIN_DIVIDE_BY_2 CLK2X option reduces the effective 311 MHz CLK2X180 DCM frequency to MHz, which is within the DCM’s frequency limits. BUFG CLKIN_DIVIDE_BY_2= TRUE CLK2X, CLK2X180 outputs DLL_FREQUENCY_MODE= LOW limited to 330 MHz, maximum. CLK_FEEDBACK= 1X 100 W IBUFDS FDCPE 622 Mbps D Q DETAILED VIEW CE LVDS/RSDS C receiver termination resistor. FDCPE_1 D Q CE C FPGA

47 Problem Re-Statement We want to build a LVDS receiver operating at 622 Mbps with a 311 MHz input clock Issues solved : Phase shifting is indirectly available at 311 MHz Receiver macros are available for Spartan-3 at 1:4, 1:6, 1:7 and 1:8 SERDES factors Setup and hold ‘eye’ parameters do still require characterization

48 XAPP462: The DCM Reference
A comprehensive 68-page “tree killer” Updated for ISE 6.3i and latest Spartan-3 DCM knowledge

49 Questions?

50 Please Fill Out and Return the Feedback Forms!
Forms are in the back of your FAE conference book Please return at back of the room Secrets of the DCM: Part 2 Steve Knapp ü Thank You! ü ü

51 Jump Point Lesson 4: Phase Shifting Lesson 5: Frequency Synthesis
Lesson 6: System vs. Source Synchronous Lesson 7: Optional CLKIN divide-by-2 Lesson 8: Spartan-3 622Mbps Design Example Session Evaluation Forms Return to last slide viewed

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