1. Wires & wire delay Lecture 9 Tuesday September 27, 2016

2. Outline September 2016Introduction to Integrated Circuit Design2 Introduction Interconnect Modeling – Wire Resistance – Wire Capacitance Introducing a distributed wire RC  -model Estimating wire RC delay assuming a dominant time constant Elmore delay model – a generalized model Handling wire branches Inserting repeaters to keep wire lengths short

3. Introduction September 2016Introduction to Integrated Circuit Design3 Chips are mostly made of wires called interconnect – In stick diagram, wires set size – Transistors are little things under the wires – Many layers of wires Wires are as important as transistors – Speed – Power – Noise Alternating layers run orthogonally Odd metal wires Even metal wires

4. Modern interconnect September 2016Introduction to Integrated Circuit Design4 Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Via 5-6 Metal 1 Local Tungsten interconnect Via 1-2

5. Choice of metals September 2016Introduction to Integrated Circuit Design5 Until 180 nm generation, most wires were aluminum Contemporary processes normally use copper – Cu atoms diffuse into silicon and damage FETs – Must be surrounded by a diffusion barrier Metal Bulk resistivity (  cm) Silver (Ag)1.6 Copper (Cu)1.7 Gold (Au)2.2 Aluminum (Al)2.8 Tungsten (W)5.3 Titanium (Ti)43.0

6. Layer stack September 2016Introduction to Integrated Circuit Design6 AMS 0.35  m process has 3 metal layers – M1 for within-cell routing – M2/M3 for vertical/horizontal routing between cells Modern processes use 6-10+ metal layers – M1: thin, narrow (< 1.5*minimum feature size) High density wiring in cells – Mid layers: thick, wide Global interconnect – Top layers: THICK, WIDE For V DD, GND, clk

7. September 2016Introduction to Integrated Circuit Design7 Sheet resistance L W L W When W=L the resistance is equal to R 0, the sheet resistance (i.e. the resistance of a square wire) A ll wires in a layer have the same thickness t t t R 0 =  /t Other books use R S Just count number of squares along wire and multiply with R S

8. Wire geometry September 2016Introduction to Integrated Circuit Design8 Old technologyModern technology w>>t Pitch = w + s t w Today: pack in many skinny wires! For long skinny wires resistance cannot be neglected since cross sectional area shrinks with feature size, wire length stays the same or increases. Hence: we need a wire RC model

9. September 2016Introduction to Integrated Circuit Design9 Example Compute the sheet resistance of a 0.22  m thick Cu wire in a 65 nm process. The resistivity of thin film Cu is 22 n . m. Find the total resistance if the wire is 0.125  m wide and 1 mm long. (Ignore the barrier layer)

10. Wire delay scaling – Local wires For local wire crossing the same amount of circuitry – Resistance stays roughly constant Length decreases by same amount as width, height stays large and/or change material to copper – Capacitance decreases by scaling factor Cap/unit length stays constant, length decreases Wire delay tracks improvement in gate delay September 2016Introduction to Integrated Circuit Design10 From Mark Horowitz at Design Automation Conference 2000 stays constant Wire length L, width W Wire length L/S, width W/S

11. Wire delay scaling – Global wires For global wire crossing the whole chip – Resistance grows linearly (with scaling factor) – Capacitance stays fixed Wire delay increases relative to gate delay September 2016Introduction to Integrated Circuit Design11 From Mark Horowitz at Design Automation Conference 2000 stays constant Wire length L, width W Wire length L, width W/S

12. Modern Interconnect September 2016Introduction to Integrated Circuit Design12 Source: Intel Global Interconnect S Local = S Technology S Global = S Die

13. Wire capacitance September 2016Introduction to Integrated Circuit Design13 Wire has capacitance c per unit length to neighbors to layers above and below Parallel plate capacitance equation C =  ox A/d  ox =  0,  ≈4 for SiO 2, low-kappa  <3 Bottom plate and fringe capacitance Note: Cap is per unit length

14. September 2016Introduction to Integrated Circuit Design14 Typical wires have ~ 0.2 fF/  m, i. e. 200 fF/mm – Compare with 1.2 fF/  m for MOSFET gate cap Metal2 Capacitance Data Metal 3 Metal 1 Data shown for s = 320, 480, 640 nm, and s = ∞

15. Wire RC delay September 2016Introduction to Integrated Circuit Design15 In any given technology wire RC increases as L 2 with wire length L r is wire resistance per unit length c is wire resistance per unit length

16. September 2016Introduction to Integrated Circuit Design16 Step-response of RC wire as a function of time and space

17. Wire delay example September 2016Introduction to Integrated Circuit Design17 Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! W N =0.78  m. W P =2W N. Assume wire cap c= 200 fF/mm, r=800  /mm from previous example 9X 1 mm long, 125 nm wide Cu wire 4X 9X driver inverter4X receiver inverter CDCD 1.4 fF R eff 2.6 fF CGCG 2.2 k  Without wire, delay becomes 5 ps*(pinv+X4/X9)=5*(0.8+4/9)= 6.2 ps

18. Wire delay example September 2016Introduction to Integrated Circuit Design18 Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! W N =0.78  m. W P =2W N. 9X 4X 9X driver inverter4X receiver inverter CDCD 1.4 fF R eff 2.6 fF CGCG 2.2 k  0.8 k  R wire What if wire resistance is added? Delay increases further with 0.7*(0.8*101.4) = 56 ps to 372 ps Without wire, delay becomes 5 ps*(pinv+X4/X9)=5*(0.8+4/9)= 6.2 ps 100 fF With wire cap, electrical effort increases with 200 fF/(9*0.36 fF) = 62 Delay becomes ~316 ps!

19. Wire delay example September 2016Introduction to Integrated Circuit Design19 Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! W N =0.78  m. W P =2W N. receiver inverter driver inverter 9X 4X 1 mm long, 125 nm wide Cu wire Wires are distributed systems Approximate with lumped element models In Spice simulations a 3-segment  -model is accurate to 3% For analytical solution: use single segment  -model

20. Elmore delay model September 2016Introduction to Integrated Circuit Design20 Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! W N =0.78  m. W P =2W N. C w /2 CDCD R eff CGCG 9X driver inverter4X receiver inverter  -wire model RwRw V0V0 Use Elmore delay model to calculate RC constant for each R: Multiply each resistance with its downstream capacitance!

21. Wire delay example September 2016Introduction to Integrated Circuit Design21 Estimate the delay of a 9X inverter driving a 4x inverter at the end of the 1 mm wire! W N =0.78  m. W P =2W N. RC product = (2.2 k  )(204 fF) + (0.8 k  )(101.4 fF) = 530 ps Propagation delay = 0.7RC = 372 ps 100 fF CDCD R eff CGCG 2.2 k  1.4 fF 0.8 k  R wire 2.6 fF X9 X4

22. Elmore delay model – from where? September 2016Introduction to Integrated Circuit Design22 Simplify the two-stage RC circuit! Write nodal equations! sC 1 sC 2 V1V1 V2V2 R1R1 R2R2 V in

23. Elmore delay model – from where? September 2016Introduction to Integrated Circuit Design23 Simplify the two-stage RC circuit! Write nodal equations! Matrix form sC 1 sC 2 V1V1 V2V2 R1R1 R2R2 V in

24. Elmore delay model – from where? September 2016Introduction to Integrated Circuit Design24 Simplify the two-stage RC circuit! sC 1 sC 2 V1V1 V2V2 R1R1 R2R2 Write nodal equations! Matrix form Invert matrix for V 1 and V 2 ! V in Characteristic equation:  =det M=0

25. Elmore delay model – from where? September 2016Introduction to Integrated Circuit Design25 Exact solution is sum of two exponentials with time constants  1 =1/s 1 and  2 =1/s 2 As you already know, poles s 1 and s 2 are often well separated! Hence,  1 >>  2 and dominating! Dominating frequency: s1s1 s2s2 Bode plot frequency Amplitude

26. Elmore delay model – from where? September 2016Introduction to Integrated Circuit Design26 C1C1 C2C2 R1R1 R2R2 V2V2 V1V1 Approximate solution: – exponential with dominating time constant  1 Each resistance is multiplied with its downstream capacitance! V in

27. Introduction to Integrated Circuit Design27 Approximative solution with dominating time constant September 2016 One example: R 1 =0.8R 2, C 1 =1.2C 2 t 1 =2.45, t 2 =0.31 Compare two-pole solution to dominating exponential

28. Elmore delay model formulation 2 September 2016Introduction to Integrated Circuit Design28 C1C1 C2C2 R1R1 R2R2 V2V2 V1V1 Alternate memory rule: This is another formulation of Elmore´s delay model: Each capacitance is multiplied with its upstream resistance.

29. Ideal wire delay September 2016Introduction to Integrated Circuit Design29 Wire delay increases as L 2 with wire length! Keep wires short! C wire /2 R 1 =0R wire V2V2 Most often  1 >>  2 and dominating! For an ideal voltage source (R 1 =0) and C 1 =C 2 =C wire /2 we get wire delay

30. Summary We have introduced a wire  -RC model We have analytically solved for delayed output response We simplified using dominant time constant We arrived at Elmore´s wire delay model! September 2016Introduction to Integrated Circuit Design30

31. 2.2 k  Using Elmore delay model September 2016Introduction to Integrated Circuit Design31 “What if I change driving capability of the X9 inverter, what driving capability will minimize the propagation.” X9 RC product = (2.2 k  )(206 fF) + (0.8 k  )(103.2 fF) = 536 ps 100 fF CDCD R eff CGCG 3.2 fF 0.8 k  R wire X9 3.2 fF R eff C G =7.2 ps, R wire C wire =160 ps → R eff =0.17 k , C G =7.2/0.17= 42 fF General RC product = R eff *(C wire +2C G )+R wire *(C wire +2C G )/2 Has minimum when R eff *C wire =R wire *C G, i.e. for slightly changed capacitance values 0.17 k  100 fF CDCD R eff CGCG 42 fF 0.8 k  R wire X118 42 fF New RC product = 0.17×(200+84)+0.8 ×( 100+42)=34+14+80+34≈160 ps

32. Using Elmore delay model September 2016Introduction to Integrated Circuit Design32 What if I cut wire in two pieces? 0.17 k  50 fF C R eff CGCG 42 fF 0.4 k  R wire X118 42 fF 0.17 k  50 fF C R eff CGCG 42 fF 0.4 k  R wire X118 42 fF + New RC product = 0.17×(100+84)+0.4 ×( 50+42)=17+14+20+17≈78 ps Total RC goes from 160 ps to 136 ps

33. Making Elmore delay model general September 2016Introduction to Integrated Circuit Design33 C1 R1 V1V1 C2 R2 V2V2 C3 R3 V 3 =V OUT “input" output V IN 1.Write nodal equations for all nodes 2.Then multiply each nodal equation with its upstream resistance from the node to the voltage source

34. Making Elmore delay model general September 2016Introduction to Integrated Circuit Design34 Elmore time constant 1 st order linear diff equation Add equations

35. Handling branches September 2016Introduction to Integrated Circuit Design35 C1 R1 V1V1 C2 R2 V2V2 C4 V4V4 C3 R3 V 3 =V OUT “input" output V IN Theory behind rule of thumb for handling branches: Modify node equation for node 2 Add equation for node 4 R4

36. Three wire segments September 2014Introduction to Integrated Circuit Design36 C 1 /2 R1R1 C 2 /2 C 3 /2 R2R2 R3R3 R0R0 Elmore´s delay formula: Each capacitance is multiplied by its upstream resistance!

37. Three wire segments with branches September 2014Introduction to Integrated Circuit Design37 Identify main path

38. Wire branches September 2014Introduction to Integrated Circuit Design38 Main path RC model; same as in previous example without branches R1R1 R2R2 R3R3 R0R0 C 1 /2 C 2 /2 C 3 /2 Alternative way of writing the same Elmore wire delay Elmore´s delay formula: As before, each capacitance is multiplied by its upstream resistance!

39. Wire branches September 2014Introduction to Integrated Circuit Design39 R1R1 R2R2 R3R3 R0R0 Add branches to RC model! C b1 /2C b2 /2C b3 /2C b1 /2C b2 /2 C b3 /2 Add delay due to branch capacitances Total delay is equal to sum of main path delay and branch contributions

40. Driving long wires with repeaters Since wire delay increases as L 2 with wire length, it could be advantageous to divide long wires into segments driven by repeaters September 2014Introduction to Integrated Circuit Design40 R w /m C w /2m R w /m C w /2m R w /m C w /2m The number of segments increase linearly as m, but the delay of each wire segment decreases as 1/m 2 Repeater data: input and output cap C rep, effective resistance R rep The delay of m segments can be written Determine the number of segments that minimizes delay: There is a critical wire length when repeaters should be considered

41. Introduction to Integrated Circuit Design41 How to size the repeater Elmore model for segment delay: R rep C rep is a constant! Two important terms for optimization: Optimum repeater strength September 2014 rep C rep R w /m C w /2m C rep rep Minimum when

42. Summing up the segment delays For m=m opt, we obtain the following wire delay September 2014Introduction to Integrated Circuit Design42

43. Conclusion Importance of wire delay Introduced distributed wire RC  -model Discussed relevance of delay equations using a dominant time constant model Using delay model to minimize wire delay Elmore delay model – a generalized model Mathematics behind Elmore model Handling branches Repeater insertion September 2016Introduction to Integrated Circuit Design43