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The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic.

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Presentation on theme: "The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic."— Presentation transcript:

1 The Wire Scaling has seen wire delays become a major concern whereas in previous technology nodes they were not even a secondary design issue. Wire parasitic effects differ from those of transistors. Wire materials could be polysilicon, aluminum, copper or diffusion materials (n+/p+). Wires of today’s processes form complex geometries that introduce capacitive, resistive and inductive parasitics. The parasitics affect circuit performance by: Increasing signal propagation delay. Contributing to energy dissipation and power distribution. Introducing extra noise sources which affect circuit reliability. A comprehensive wire model is very complex

2 The Wire Inter wire parasitics create coupling effects between the different bus signals. A simplified wire model has: The inductive effects ignored since it is assumed that the resistance of the wire is large. The short wires must have large cross-sections or low resistivity. Separation between neighboring wires is assumed to be large or wires that are close to each other run together only for a short distance. With these conditions inter wire capacitance can be ignored and all parasitic capacitances modeled as a capacitor to ground :- the lumped capacitance model. Current Flow L W H dielectric tdi substrate

3 The Wire Capacitance In the diagram shown, the width of the wire (W) is substantially larger than the thickness of the insulating material. The electric field lines are assumed to be perpendicular to the capacitor plates. The wire capacitance can be modeled as a parallel plate capacitor. The dielectric of choice is SiO2. With scaling and increasingly dense circuits, the wires are placed close to each other. The proximity of the wires make fringing capacitance to become more dominant. W H cfringe cpp

4 Wire Capacitance The fringing capacitance Cfringe is modeled using cylindrical wire with a dimension equal to the interconnect thickness H. The approximation of the wire capacitance is: The lumped C wire model is not complete for today’s technologies since the wire is not completely isolated from its surrounding structures and is thus not only capacitively coupled to ground. Not all of the capacitive components terminate at ground, many connect to other wires. parallel

5 Wire Resistance The resistance of the wire is given by:
A rectangular wire is assumed. ρ is the resistivity of the material measured in Ω-m. Rho is constant in a given technology and leads to the modification of the equation as follows: R = RsquareL/W Rsquare is ρ/H and is the sheet resistance of a material having units of ohms per square (Ω/square) At high frequencies a phenomenon called skin effect comes into play and resistance becomes frequency dependent. Skin effect is an issue in wider wires. Current crowds at the wire edges. H

6 Wire Indctance Consequences of on-chip inductance include:
Signal ringing Over-shoot Signal reflection due to impedance mismatch Inductive coupling between lines Switching noise due to Ldi/dt voltage drops. The inductance of a section of a circuit can be evaluated as V = Ldi/dt Inductance per unit length of wire and capacitance C are related by the expression CL=ε. An ideal wire assumes that a voltage change at one end of the wire propagates immediately to the wire’s other end. The wire becomes equipotential. This ideal approach still holds for short wires, also designers interested only in circuit behavior can use this ideal model. Circuit parasitics of a wire are distributed along its length instead of being lumped at a single position. With low to medium switching frequencies and small resistive components we can consider only a lumped capacitive component of wire.

7 Lumped C Wire Model This is a simple but yet effective model and widely used in digital design. There is a need to include the resistive as well as the capacitive components. We can lump the total wire resistance into a single R and the global capacitance into a single C. The lumped RC model is inaccurate for long interconnects. The RC network can enhance understanding of a distributed RC network. In order to evaluate the RC model we use the RC tree which has: Has a single input node S. Has all capacitors between a node and ground. Has no resistive loops Vout Cwire Driver Vout RDriver CLumped Source

8 The Lumped RC Model The resistive-capacitive (RC) model.
R1 is the common resistance in the path. There is a unique resistive path between the source node S and any node i on the network A shared path resistance from the root node to nodes k and i is: The equation describes the common resistance from input to nodes i and k. R2 2 R4 C2 S 1 R3 4 R1 3 Ri C4 C1 i C3 Ci R2 R1 C2 R3 C1 C3

9 The Elmore Delay Model If we have a step input and if we assume that all nodes are initially at logic 0 we have: The Elmore Delay Model offers designers a quick estimate of the delay. To compute the time constant of a wire of length L, we partition the wire into N identical segments. Each segment has a length of L/N. The segment resistance becomes r(L/N). The segment’s capacitance becomes c(L/N). The above equation calculates the time constant of the wire using the Elmore Delay Model. For rL = R and cL = C we have the Lumped R and C. If there are numerous segments (N Large) the RC model approaches that of a distributed RC line with:

10 The Elmore Delay Model Vin rL Vj-1 rL Vj rL rL Vout The delay of a wire is a quadratic function of its length i.e. doubling the length of a wire quadruples its delay. The lumped RC model underestimates the delay by 0.5 times. The Elmore Delay model only estimates the value of the dominant component. We have discussed briefly that the Elmore Model can be used to estimate the delay complex transistor netwworks. Find the voltage at node i? Find the response at node i with respect to time? As the number of segments in the network becomes large with sections becoming smaller we have: Vj+1 cL cL cL cL Ij-1 Ij Ij+1

11 The Diffusion Equation
The variable x in the previous equation is the distance from the input to the point of interest. The variable r is the resistance per unit length. c is the capacitance per unit length. V is the voltage at the particular point on the wire. The equation has no closed form solution. The solution for the propagation of a voltage step along the wire shows that the rise/fall delay tx along a wire of length x is: tx=kx2. k is a constant given by: E is given by: The mass m and the velocity c2 are the variables of this equation. The equation results from a discrete analysis of the circuit with n being the number of sections. The 0.7 factor accounts for the rise and/or fall delay to half rail.

12 The Diffusion Equation
As n becomes very large i.e. individual sections become very small we have: The discussed wire delays have significant bearing on circuit performance and when the propagation delay of the wire is greater than the propagation delay of the gate (tpRC>tpgate) that’s cause for concern. The critical length of a wire is described by: So far the inductance of the wire has been negligible, but when the circuits switch fact and the interconnect wire is of high quality the inductance of the wire starts to dominate delay behavior. At this point transmission line effects have to be considered. Inductance is distributed over the wire just like resistance and capacitance. The distributed rlc model describes the transmission line.

13 The transmission Line The transmission line is the most accurate approximation of actual interconnect behavior. The signal now propagates over a wire like a wave. This is different from the distributed rc model in which the signal diffuses from source to destination. As a wave the signal propagates by alternatively transferring energy from the electric field to the magnetic field. In simple terms energy is transferred between capacitive (electric field) and inductive (magnetic field) modes. At point x at time t we have: The leakage conductance is assumed to be 0.

14 The Transmission Line First: assume that the resistance of the line is negligible. The result is a lossless transmission line. No voltage drops just a capacitive-inductive (cl) model. The wave propagation equation becomes: A step input applied to a lossless transmission line propagate along the line with a speed: The behavior of the transmission line is influenced by the termination of the line. Line termination determines how much the wave is reflected upon arrival at the end of the wire. This would be capacitive termination since the line is lc. Chip interconnects are not wide enough to be treated as lossless transmission lines. The resistance of an interconnect is an important factor. The response of a lossy transmission line to a unit step function combines wave propagation with a diffusion component.

15 The Lossy Transmission Line
The diffusive component affects the amplitude of the signal. If the resistive component becomes dominant then the line behaves like a distributed rc. The transmission line effects are used when tr and tf are smaller than the time of flight. The wire’s total resistance must be restricted to R<5Z0 for transmission line effects to be considered. If this is not the case then the distributed RC model is sufficient. The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance or when R<Z0/2.

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