# EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

## Presentation on theme: "EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design."— Presentation transcript:

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE5900 Advanced Algorithms for Robust VLSI CAD

EE141 © Digital Integrated Circuits 2nd Wires 2 Modern Interconnect

EE141 © Digital Integrated Circuits 2nd Wires 3 Modern Interconnect - II

EE141 © Digital Integrated Circuits 2nd Wires 4 0.18 Source: Gordon Moore, Chairman Emeritus, Intel Corp. 0 50 100 150 200 250 300 Technology generation (  m ) Delay (psec) Transistor/Gate delay Interconnect delay 0.80.50.25 0.15 0.35 Interconnect Delay Dominates

EE141 © Digital Integrated Circuits 2nd Wires 5 Wire Model

EE141 © Digital Integrated Circuits 2nd Wires Capacitor  A capacitor is a device that can store an electric charge by applying a voltage  The capacitance is measured by the ratio of the charge stored to the applied voltage  Capacitance is measured in Farads

EE141 © Digital Integrated Circuits 2nd Wires 3D Parasitic Capacitance  Given a set of conductors, compute the capacitance between all pairs of conductors. - - - - - - - + + + + + C=Q/V 1V1V

EE141 © Digital Integrated Circuits 2nd Wires Simplified Model  Area capacitance (Parallel plate): area overlap between adjacent layers/substrate  Fringing/coupling capacitance:  between side-walls on the same layer  between side-wall and adjacent layers/substrate m2 m1 m3

EE141 © Digital Integrated Circuits 2nd Wires 9 The Parallel Plate Model (Area Capacitance) Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation

EE141 © Digital Integrated Circuits 2nd Wires Wire Capacitance  More difficult due to multiple layers, different dielectric m2 m1 m3  =3.9  =8.0  =4.0  =4.1 multiple dielectric

EE141 © Digital Integrated Circuits 2nd Wires Simple Estimation Methods - I  C = Ca*(overlap area) +Cc*(length of parallel run) +Cf*(perimeter)  Coefficients Ca, Cc and Cf are given by the fab  Cadence Dracula  Fast but inaccurate

EE141 © Digital Integrated Circuits 2nd Wires Simple Estimation Methods - II  Consider interaction between layer i and layers i+1, i+2, i–1 and i–2  Consider distance between conductors on the same layer  Cadence Silicon Ensemble  Accuracy  50%

EE141 © Digital Integrated Circuits 2nd Wires Library Based Methods  Build a library of tens of thousands of patterns and compute capacitance for each pattern  Partition layout into blocks, and match with the library  Accuracy  20%

EE141 © Digital Integrated Circuits 2nd Wires Accurate Methods In Industry  Finite difference/finite element method  Most accurate, slowest  Raphael  Boundary element method  FastCap, Hicap

EE141 © Digital Integrated Circuits 2nd Wires 15 Fringing versus Parallel Plate Fringing/Coupli ng capacitance dominates.

EE141 © Digital Integrated Circuits 2nd Wires Wire Resistance  Basic formula R=(  /h)(l/w)   : resistivity  h: thickness, fixed for a given technology and layer number  l: conductor length  w: conductor width h l w

EE141 © Digital Integrated Circuits 2nd Wires Typical Rs (Ohm/sq) MinTypicalMax M1, M20.050.070.1 M3, M40.030.040.05 Poly152030 Diffusion1025100 N-well100020005000

EE141 © Digital Integrated Circuits 2nd Wires 18 Contact and Via  Contact:  link metal with diffusion (active)  Link metal with gate poly  Via:  Link wire with wire  Overlapping two layers (diffusion, gate poly or metal) and providing a contact hole filled with metal  Substrate Contact and Well Contact:  Link substrate or well to supply voltage

EE141 © Digital Integrated Circuits 2nd Wires 19 Interconnect Delay

EE141 © Digital Integrated Circuits 2nd Wires Analysis of Simple RC Circuit state variable Input waveform ± v(t) C R v T (t) i(t)

EE141 © Digital Integrated Circuits 2nd Wires Analysis of Simple RC Circuit Step-input response: match initial state: output response for step-input: v0v0 v 0 u(t) v 0 (1-e -t/RC )u(t)

EE141 © Digital Integrated Circuits 2nd Wires 0.69RC  v(t) = v 0 (1 - e -t/RC ) -- waveform under step input v 0 u(t)  v(t)=0.5v 0  t = 0.69RC  i.e., delay = 0.69RC (50% delay) v(t)=0.1v 0  t = 0.1RC v(t)=0.9v 0  t = 2.3RC  i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)  For simplicity, industry uses T D = RC (= Elmore delay)  We use both RC and 0.69RC in this course.

EE141 © Digital Integrated Circuits 2nd Wires Elmore Delay Delay 1.50%-50% point delay 2.Delay=RC (Precisely, 0.69RC)

EE141 © Digital Integrated Circuits 2nd Wires 24 Elmore Delay - III What is the delay of a wire?

EE141 © Digital Integrated Circuits 2nd Wires 25 Elmore Delay – IV Assume: Wire modeled by N equal-length segments For large values of N: Precisely, should be 0.69RC/2

EE141 © Digital Integrated Circuits 2nd Wires Elmore Delay - V 26 n1 n2 C/2 R n1 n2 R=unit wire resistance*length C=unit wire capacitance*length

EE141 © Digital Integrated Circuits 2nd Wires RC Tree Delay 27 27 2 2 1 1 3.5 Unit wire cap=1, unit wire res=1 4 2 7 4 2*(1+3.5+3.5+2+2)=24 24+7*3.5=48.5 24+4*2=32 RC Tree Delay=max{32,48.5}=48.5 Precisely, 0.69*48.5

EE141 © Digital Integrated Circuits 2nd Wires Summary  Wire capacitance  Fringing/coupling capacitance dominates area capacitance  Wire resistance  RC Elmore delay model for wire  For single wire, 0.69RC/2  RC tree

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