1. Appendix C Basics of Logic Design

2. Appendix C — Logic Basic — 2 Logic Design Basics §4.2 Logic Design Conventions Objective: To understand how to build a processor 32 operation result a b ALU Program in C++ Compiler + Assemble r

3. Appendix C — Logic Basic — 3 Logic Design Basics §4.2 Logic Design Conventions Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store information

4. Appendix C — Logic Basic — 4 Combinational and Sequential Logic §4.2 Logic Design Conventions Combinational logic: A logic system whose blocks do not contain memory and hence compute the same output given the same input. Sequential logic A group of logic elements that contain memory and hence whose value depends on the inputs as well as the current contents of the memory.

5. Appendix C — Logic Basic — 5 Combinational Elements AND-gate Y = A & B A B Y I0 I1 Y MuxMux S Multiplexer Y = S ? I1 : I0 A B Y + A B Y ALU F Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B)

6. Appendix C — Logic Basic — 6 Combinational Elements Output is completely specified by the input TRUTH TABLE is a way of describing how an output of a combinational logic depends on the input – completely specifies the logic function Example: Basic logic function such as AND INPUTOUTPUT ABY 100 010 000 111 How many entries in a truth table?

7. Appendix C — Logic Basic — 7 Truth Table

8. Appendix C — Logic Basic — 8 Boolean Algebra Alternate way to represent logical functions: Use Boolean Algebra to express logical functions as logical equations

9. Appendix C — Logic Basic — 9 Laws of Boolean Algebra

10. Appendix C — Logic Basic — 10 DeMorgan’s Theorem

11. Appendix C — Logic Basic — 11 Logic Equations

12. Appendix C — Logic Basic — 12 Logic Equations

13. Appendix C — Logic Basic — 13 Logic Equations

14. Appendix C — Logic Basic — 14 Gates Any logical function can be constructed using AND gates, OR gates, and inversion.

15. Appendix C — Logic Basic — 15 Gates How do you realize the following logic function using gates?

16. Appendix C — Logic Basic — 16 Gates Another way to realize the same logic function? Using DeMorgan’s Theorem

17. Appendix C — Logic Basic — 17 Gates

18. Appendix C — Logic Basic — 18 Larger Logic Blocks

19. Appendix C — Logic Basic — 19 Multiplexor

20. Appendix C — Logic Basic — 20 Sum of Product Can we convert this into Product of Sum form?

21. Appendix C — Logic Basic — 21 Product of Sum

22. Appendix C — Logic Basic — 22 Truth Table to Sum of Product

23. Appendix C — Logic Basic — 23 Programmable Logic Array (PLA)

24. Appendix C — Logic Basic — 24 Programmable Logic Array (PLA) Show the PLA implementation using (a) dots diagram, and (b) Gates for the following truth table

25. Appendix C — Logic Basic — 25 Programmable Logic Array (PLA)

26. Appendix C — Logic Basic — 26 Programmable Logic Array (PLA)

27. Appendix C — Logic Basic — 27 Don’t Care

28. Appendix C — Logic Basic — 28 Don’t Care

29. Appendix C — Logic Basic — 29 Array of Logic Elements

30. Appendix C — Logic Basic — 30 1-Bit ALU

31. Appendix C — Logic Basic — 31 1-Bit ALU

32. Appendix C — Logic Basic — 32 1-Bit ALU

33. Appendix C — Logic Basic — 33 32-Bit ALU

34. Appendix C — Logic Basic — 34 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Clk Q D Q

35. Appendix C — Logic Basic — 35 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later D Clk Q Write D Q Clk

36. Appendix C — Logic Basic — 36 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period

37. Appendix C — Logic Basic — 37 Basic Memory Element

38. Appendix C — Logic Basic — 38 D Latch

39. Appendix C — Logic Basic — 39 D Flip Flop

40. Appendix C — Logic Basic — 40 D Flip Flop

41. Appendix C — Logic Basic — 41 Register File

42. Appendix C — Logic Basic — 42 Register File – Read Port

43. Appendix C — Logic Basic — 43 Register File – Write Port

44. Appendix C — Logic Basic — 44 SRAM Memory

45. Appendix C — Logic Basic — 45 SRAM Memory

46. Appendix C — Logic Basic — 46 SRAM Memory

47. Appendix C — Logic Basic — 47 DRAM Memory