1. ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 2: Overview of Computer Organization Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by Patterson at Berkeley, Ryan Kastner at UCSB and Mary Jane Irwin at Penn State

2. “Von-Neumann” Computer Processor Computer Control Datapath Memory (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running) Store –programmed concept was not invented by John von Neumann only Other inventors Presper Eckert and John Mauchly ENIAC 1943 University of Pensilvania ECE 15B Spring 2010

3. Need Many Layers to Handle Complexity ECE 15B Spring 2010 I/O systemProcessor Compiler Operating System (Mac OSX) Application (ex: browser) Digital Design Circuit Design Instruction Set Architecture Datapath & Control transistors Memory Hardware Software Assembler Layers of Abstraction This class is about this region

4. Below the Program lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) High Level Language Program (e.g., C) Assembly Language Program (e.g.,MIPS) Machine Language Program (MIPS) Hardware Architecture Description (e.g., block diagrams) Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Logic Circuit Description (Circuit Schematic Diagrams) Architecture Implementation

5. Review: Unsigned Binary Representation HexBinaryDecimal 0x000000000…00000 0x000000010…00011 0x000000020…00102 0x000000030…00113 0x000000040…01004 0x000000050…01015 0x000000060…01106 0x000000070…01117 0x000000080…10008 0x000000090…10019 … 0xFFFFFFFC1…1100 0xFFFFFFFD1…1101 0xFFFFFFFE1…1110 0xFFFFFFFF1…1111 2 32 - 1 2 32 - 2 2 32 - 3 2 32 - 4 2 32 - 1 1 1 1... 1 1 1 1 bit 31 30 29... 3 2 1 0 bit position 2 31 2 30 2 29... 2 3 2 2 2 1 2 0 bit weight 1 0 0 0... 0 0 0 0 - 1 ECE 15B Spring 2010

6. Data input: Analog  Digital Real world is analog! To import analog information, we must do two things – Sample E.g., for a CD, every 44,100ths of a second, we ask a music signal how loud it is. – Quantize For every one of these samples, we figure out where, on a 16-bit (65,536 tic-mark) “yardstick”, it lies. www.joshuadysart.com/journal/archives/digital_sampling.gif ECE 15B Spring 2010

7. Logic Design Basics Information encoded in binary – Low voltage = 0, High voltage = 1 – One wire per bit – Multi-bit data encoded on multi-wire buses ECE 15B Spring 2010

8. Grouping of signals ECE 15B Spring 2010

9. Why binary? Other logic styles allow for implementations of multilevel logic (e.g. threshold logic) CMOS digital design style, which is the most power efficient and therefore currently dominating, enforces binary signal representation ECE 15B Spring 2010

10. The lowest layer of hierarchy ECE 15B Spring 2010

11. How to build combinational elements? AND-gate – Y = A & B A B Y I0 I1 Y MuxMux S Multiplexer Y = S ? I1 : I0 A B Y + A B Y ALU F Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B) ECE 15B Spring 2010

12. Gate level design: NAND

13. N instances of 1-bit wide multiplexor ECE 15B Spring 2010

14. 1-bit-wide multiplexor ECE 15B Spring 2010

15. Implementation of 1-bit-wide multiplexor ECE 15B Spring 2010

16. 4-to-1 multiplexor ECE 15B Spring 2010

17. Hierarchical construction of MUXes ECE 15B Spring 2010

18. Building adder ECE 15B Spring 2010

19. Building adder ECE 15B Spring 2010

20. Building adder ECE 15B Spring 2010

21. Ripple carry adder ECE 15B Spring 2010

22. Circuit delay ECE 15B Spring 2010

23. Simple ALU ECE 15B Spring 2010

24. Combinational logic Complex logic blocks are built from basic AND, OR, NOT building blocks we will see shortly A combinational logic block is one in which the output us a function only of its current input Combination logic cannot have memory ECE 15B Spring 2010

25. Sequential logic = Flip Flops + combination logic ECE 15B Spring 2010

26. How to implement? ECE 15B Spring 2010

27. Will that work?

28. Sequential Elements Flip flop: stores data in a circuit – Uses a clock signal to determine when to update the stored value – Edge-triggered: update when Clk changes from 0 to 1 D Clk Q D Q ECE 15B Spring 2010

29. Sequential Elements Flip flop with write control – Only updates on clock edge when write control input is 1 – Used when stored value is required later D Clk Q Write D Q Clk ECE 15B Spring 2010

30. Register ECE 15B Spring 2010

31. D flip flop gate design ECE 15B Spring 2010

32. Second try for previous example

33. Clock rate (clock cycles per second in MHz or GHz) is inverse of clock cycle time (clock period) CC = 1 / CR one clock period 10 nsec clock cycle => 100 MHz clock rate 5 nsec clock cycle => 200 MHz clock rate 2 nsec clock cycle => 500 MHz clock rate 1 nsec (10 -9 ) clock cycle => 1 GHz (10 9 ) clock rate 500 psec clock cycle => 2 GHz clock rate 250 psec clock cycle => 4 GHz clock rate 200 psec clock cycle => 5 GHz clock rate Clock + sequential logic = synchronous design ECE 15B Spring 2010

34. Clocking Methodology Combinational logic transforms data during clock cycles – Between clock edges – Input from state elements, output to state element – Longest delay determines clock period ECE 15B Spring 2010

35. CPU Overview ECE 15B Spring 2010

36. … with muxes Can’t just join wires together Use multiplexers ECE 15B Spring 2010

37. … with muxes ECE 15B Spring 2010