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Digital Logic Vol. 2 Presented by Leo Pleše ScienceUp.org.

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Presentation on theme: "Digital Logic Vol. 2 Presented by Leo Pleše ScienceUp.org."— Presentation transcript:

1 Digital Logic Vol. 2 Presented by Leo Pleše ScienceUp.org

2 Sequential logic

3 Latches asynchronous flip-flops SR latch NOR NAND SRQstate 001 / 00 / 1 hold state 0101reset 1010set 11 X (not used) Qstate 00 X (not used) 0110reset 1001set 111 / 00 / 1 hold state

4 Synchronous latch synchronous SR latch / clocked SR flip-flop gated SR latch level-sensitive/triggered E (clock)state 0no change 1same as SR latch

5 Synchronous flip-flops edge-triggered – increasing (rising) / decreasing (falling) edge clock input Types: synchronous SR latch = SR flip-flop D-type T-type JK-type

6 D-type (data / delay) FF rising edge-triggered base for shift registers ClockD rising edge00 11 non rising edge XQ

7 T-type (toggle) FF TQstate 000hold state 011 101toggle 110

8 JK-type FF J = SK = RQstate 0000hold state 0100reset 1001set 1101toggle 0011hold state 0110reset 1011set 1110toggle

9 Thanks for watching!

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