Presentation is loading. Please wait.

Presentation is loading. Please wait.

Rise and rise again until lambs become lions 授課老師:伍紹勳 課程助教:邱麟凱、江長庭.

Similar presentations


Presentation on theme: "Rise and rise again until lambs become lions 授課老師:伍紹勳 課程助教:邱麟凱、江長庭."— Presentation transcript:

1 Rise and rise again until lambs become lions 授課老師:伍紹勳 課程助教:邱麟凱、江長庭

2 Rise and rise again until lambs become lions Outlines Sequential logic circuits – Memory and Clock SR latch D Flip-Flop Lab

3 Rise and rise again until lambs become lions Sequential logic circuits Combinational logic circuits – depends only on current inputs Sequential logic circuits – depends on past and current inputs Memory and Clock!!

4 Rise and rise again until lambs become lions SR Latch SR Latch (Memory) – Steady state results R S Q Q’ InputFunction S = 1 , R = 0Set ( Q 設為 1 ) S = 0 , R = 1Reset ( Q 設為 0 ) S = 1 , R = 1Hold ( Q 保持不變 ) S = 0 , R = 0 不被允許的輸入 R S Q Q’ R S Q R S Q 1 1 Q

5 Rise and rise again until lambs become lions Clock When to set and reset How to synchronize devices with memory – Positive (rising) edge triggered – Negative (falling) edge triggered time

6 Rise and rise again until lambs become lions Flip Flops Input type – SR 、 D 、 JK 、 T Trigger type – Rising(positive)-edge – Falling(negative)-edge

7 Rise and rise again until lambs become lions D-type positive edge triggered FF R S D Clock Q Q’ SR Latch

8 Rise and rise again until lambs become lions D Flip Flop R S D Clock Clock = 1, D: X->X’ R S D Clock Clock: 0->1 R S D Clock Clock = X’ X 0->1 1->X’ 1->X X’ X X 1 X X’->1 X->X X X->X’ S, R = 1  Hold S = X, R = X’  Set the latchas X S, R will not change with D

9 Rise and rise again until lambs become lions Lab Today’s target: D-type positive edge triggered Flip-Flop IC : 7400 (NAND) x 2 、 LED x 1 How to realize three-inputs NANDs with two-inputs NANDs? 3


Download ppt "Rise and rise again until lambs become lions 授課老師:伍紹勳 課程助教:邱麟凱、江長庭."

Similar presentations


Ads by Google