1. Date of download: 6/3/2016 Copyright © 2016 SPIE. All rights reserved. Overlay budget analysis of gate layer for sub-60-nm memory device. Scanner contributions are around 44% of the total budget. Figure Legend: From: Application results of lot-to-lot high-order and per-shot overlay correction for sub- 60-nm memory device fabrication J. Micro/Nanolith. MEMS MOEMS. 2009;8(3):033008-033008-4. doi:10.1117/1.3210241

2. Date of download: 6/3/2016 Copyright © 2016 SPIE. All rights reserved. Schematic of high-order wafer correction (HOWC). In HOWC, high-order polynomial fitting is implemented, mainly for wafer correction, instead of linear correction in this particular experiment. Figure Legend: From: Application results of lot-to-lot high-order and per-shot overlay correction for sub- 60-nm memory device fabrication J. Micro/Nanolith. MEMS MOEMS. 2009;8(3):033008-033008-4. doi:10.1117/1.3210241

3. Date of download: 6/3/2016 Copyright © 2016 SPIE. All rights reserved. Three sigma residual improvement after third-order wafer correction. Amount of improvement is defined as the difference of mean values between two groups; those are linear correction group and high-order correction group. Positive sign implies improvement, while negative sign means getting worse. Figure Legend: From: Application results of lot-to-lot high-order and per-shot overlay correction for sub- 60-nm memory device fabrication J. Micro/Nanolith. MEMS MOEMS. 2009;8(3):033008-033008-4. doi:10.1117/1.3210241

4. Date of download: 6/3/2016 Copyright © 2016 SPIE. All rights reserved. Overlay error is scan-direction (routing) dependent. If there are scan direction differences between the previous and current layer, overlay error can be amplified depending on scan-direction (left-right or up-down). High-order correction cannot compensate for this kind of error because there are abrupt vector direction changes between adjacent shots. Figure Legend: From: Application results of lot-to-lot high-order and per-shot overlay correction for sub- 60-nm memory device fabrication J. Micro/Nanolith. MEMS MOEMS. 2009;8(3):033008-033008-4. doi:10.1117/1.3210241

5. Date of download: 6/3/2016 Copyright © 2016 SPIE. All rights reserved. Schematic of per-shot-correction (PSC). In PSC, shot correction is implemented for each shot with different correction parameter values. Figure Legend: From: Application results of lot-to-lot high-order and per-shot overlay correction for sub- 60-nm memory device fabrication J. Micro/Nanolith. MEMS MOEMS. 2009;8(3):033008-033008-4. doi:10.1117/1.3210241

6. Date of download: 6/3/2016 Copyright © 2016 SPIE. All rights reserved. Experimental results of PSC. Overlay error due to scan-direction difference is clearly improved with PSC. Figure Legend: From: Application results of lot-to-lot high-order and per-shot overlay correction for sub- 60-nm memory device fabrication J. Micro/Nanolith. MEMS MOEMS. 2009;8(3):033008-033008-4. doi:10.1117/1.3210241