1. Tezzaron Semiconductor 03/18/101 Advances in 3D Bob Patti, CTO rpatti@tezzaron.com

2. Tezzaron Semiconductor 03/18/102 A Closer Look at Wafer-Level Stacking Dielectric(SiO2/SiN) Gate Poly STI (Shallow Trench Isolation) Oxide Silicon W (Tungsten contact & via) Al (M1 – M5) Cu (M6, Top Metal) “ Super-Contact ”

3. Tezzaron Semiconductor 03/18/103 Next, Stack a Second Wafer & Thin:

4. Tezzaron Semiconductor 03/18/104 Two wafer Align & Bond Course Grinded Fine Grinded After CMPSi Recessed Stacking Process Sequential Picture Misalign=0.3um Top wafer Bottom wafer High Precision Alignment

5. Tezzaron Semiconductor 03/18/105 3rd wafer 2nd wafer 1st wafer: controller Then, Stack a Third Wafer:

6. Tezzaron Semiconductor 03/18/106 1st wafer: controller 2nd wafer 3rd wafer Finally, Flip, Thin & Pad Out: This is the completed stack!

7. Tezzaron Semiconductor 03/18/107 3 rd Si thinned to 5.5um 2 nd Si thinned to 5.5um 1 st Si bottom supporting wafer SiO 2

8. Tezzaron Semiconductor 03/18/108 3D Interconnect Characteristics SuperContact TM II 200mm Via First, FEOL SuperContact TM 200mm Via First, FEOL SuperContact TM 300mm Via First, FEOL Bond PointsChip to Wafer Size L X W X D Material 0.85  X 0.85  X 5.5  W 1.2  X 1.2  X 6.0  W 1.6  X 1.6  X 10.0  W 1.7  X 1.7  Cu 15  X 15  Cu Minimum Pitch 1.75  <2.5  <3.2  2.4  (1.1  25   Feedthrough Capacitance 2fF2-3fF6fF<<<25fF Series Resistance <1.5  <0.6  <1.5  <<

9. Tezzaron Semiconductor 03/18/109 Main Memory Power Cliff DDR3 ~40mW per pin 1024 Data pins →40W 4096 Data pins →160W Die on Wafer ~24uW per pin

10. Tezzaron Semiconductor 03/18/1010 The Industry Issue DDR2/3/4 Memory Channels  To continue to increase CPU performance, exponential bandwidth growth required.  More than 200 CPU cycles of delay to memory results in cycle for cycle CPU stalls.  16 to 64 Mbytes per thread required to hide CPU memory system accesses.  No current extension of existing IC technology can address requirements.  Memory I/O power is running away. Need 50x bandwidth improvement. Need 10x better cost model than embedded memory.

11. Tezzaron Semiconductor 03/18/1011 The “Killer” App: Split-Die  Embedded Performance with far superior cost/density.  110nm DRAM node has better density than 45nm embedded DRAM.  1000x reduction in I/O power. I/O Pad area : Bumping or wire bonding Customer Device DRAM Tezzaron 3D DRAM Proven Technology!

12. Tezzaron Semiconductor 03/18/1012 Coming Soon…

13. Tezzaron Semiconductor 03/18/1013 Logic on Memory 172 pads 92 pads (528 total pads at edge, stagger 250um pad, 125um pitch ~1500 available pads) 199 I/O Bondpoints/side 8 DRAM ports 16x21 pad array

14. Tezzaron Semiconductor 03/18/1014 DRAM Die “extra TSVs” ~40,000 in the core area ~250,000 on periphery “extra TSVs” ~100,000 in the core area ~50,000 in gap Customer circuits

15. Tezzaron Semiconductor 03/18/1015 Current Memory Split-Die Projects

16. Tezzaron Semiconductor 03/18/1016 MPW

17. Tezzaron Semiconductor 03/18/1017 MPW for Hyper-Integration 5 layer stacks Layer5 Layer7 Layer9 Layer Poly91117 Copper Wire21 (25)32 (38)34 (42) Al/W Wire7713 Trans. Count2.5B2.6B5B

18. Tezzaron Semiconductor 03/18/1018 Cut Away View

19. Tezzaron Semiconductor 03/18/1019 Stack of Stacks Assembly Participant 2 layer logic device Face to Face Bond 5x2.5,5,12.5 mm Octopus memory device 21.8x12.3 mm (2 -5 layer) Bond pads 528 available Stagger 125um pitch Controller Memory TSVs

20. Tezzaron Semiconductor 03/18/1020 SiCB Design Targets

21. Tezzaron Semiconductor 03/18/1021 Metal Interconnect Data All metals are copper 2 thin and 1 thick metal on top side 1 thin metal on backside 6um oxide separation between metal layers 6um oxide separation between metal 1 and substrate Target Cap 0.08pf/mm for min width Metal 1, 2 and backside metal. Resistance for min width thin metals is ~2.5mΩ/um Resistance for min width thick metals is ~80uΩ/um Thin metal 6.25/6.25um line/space Thick metal 12.5/12.5um line/space

22. Tezzaron Semiconductor 03/18/1022 TSV Characteristics TSV Current capacity 500mA DC TSV Resistance ~200uΩ TSV cut angle ~88.5°

23. Tezzaron Semiconductor 03/18/1023 Metal Stack Cut Away 12.5um/12.5um/25um 6.25um/6.25um/1.5umMin Width/Min Space/ Thickness6um oxide 350um Si Substrate

24. Tezzaron Semiconductor 03/18/1024 Cut Away with TSV Top thick metal and via are formed together 85um landing TSV is conformal 85um cut Taper to 65um at bottom 350um Si Substrate

25. Tezzaron Semiconductor 03/18/1025 Bonded Wafer Pair Actual wafer gap is <1um 350um Si Substrate

26. Tezzaron Semiconductor 03/18/1026 Silicon Circuit Boards SiCB 1 SiCB 2 SiCB 1 Memory Buffer Processing element

27. Tezzaron Semiconductor 03/18/1027 DRC, LVS, Transistor synthesis, Crossprobing. Multiple tapeouts, 0.35um-45nm >20GB, ~10B devices

28. Tezzaron Semiconductor 03/18/1028 Possible Magma 3D Roadmap Today: Quartz DRC in deployment at Tezzaron for 3D designs Quartz LVS in alpha testing to finish 3D support Today: Quartz DRC in deployment at Tezzaron for 3D designs Quartz LVS in alpha testing to finish 3D support March 2010 June 2010Oct 201020112012 Talus 1.2 Talus Vortex FX Hydra 1.2 Talus Vortex FX Hydra 1.2 2010: Development of 3D data model Implement 3D data model across platform Define partitioning cost functions and prototype 2010: Development of 3D data model Implement 3D data model across platform Define partitioning cost functions and prototype 2011: Deploy 3D tool box for users Alpha testing on automated 3D solution – partitioning & synthesis “2.5D solution” 2011: Deploy 3D tool box for users Alpha testing on automated 3D solution – partitioning & synthesis “2.5D solution” 2012: Deploy automated 3D solution 2012: Deploy automated 3D solution 3D Designer 3D Toolbox 3D Quartz DRC/LVS Finesim Titan Talus 1.1 Hydra 1.1 Tekto n 3D Quartz DRC/LVS Finesim Titan Talus 1.1 Hydra 1.1 Tekto n

29. Tezzaron Semiconductor 03/18/1029 3D Issues Highly complex supply chain –2 chips, 6 designs, 5 fabs, 6 mask sets –ETS/ Alignment keys New design issues –2.3M ports for LVS Material information exchange 3D construction information –Orientation, notch location –Front view, back view, fab view, wafer view

30. Tezzaron Semiconductor 03/18/1030 Industry Trends Cu, Ni, W TSVs –Lots of Cu activity Who does the 3D assembly? Big test concerns Tools are coming on line –Magma –Synopsis

31. Tezzaron Semiconductor 03/18/1031 Now –CMOS Sensors (1/2 Layer) Near term –Memory (2/4/8 Layer) –Logic/memory combo Next 2-3 years –Mixed signal/logic –Smart(er) Power 5 years –Logic/Logic Commercialization

32. Tezzaron Semiconductor 03/18/1032 Other Developments 9 metal layers Backside inductors Backside metal alignment now 0.5um 300mm by year end White light frontside to frontside alignment First SVTC processed Al test wafers out of fab 3/17/10 –Copper due out 3/19/10 Improved chip to wafer work on going –3-5um target alignment

33. Tezzaron Semiconductor 03/18/1033 Other Developments 28 3D devices completed or in fab 20 more devices will go into fab in April SOI with 0.35um TSVs in review Transition TSVs to “normal” process Customer 4 layer logic going into fab in April –Then it will be chip to wafer stacked

34. Tezzaron Semiconductor 03/18/1034 An Illustration: CPU/Memory Stack R8051 CPU –80MHz operation; 140MHz Lab test (VDD High) –220MHz Memory interface IEEE 754 Floating point coprocessor 32 bit Integer coprocessor 2 UARTs, Int. Cont., 3 Timers, … Crypto functions 128KBytes/layer main memory 5X performance 1/10 th Power