1. Research Interests  NOCs – Networks-on-Chip  Embedded Real-Time Software  Real-Time Embedded Operating Systems (RTOS)  System Level Modeling and Synthesis  Multi-core architecture for networks and Systems on Chip (SoCs)  Asynchronous and GALS Circuits  Digital Systems Fast Prototyping (with FPGAs)  Reconfigurable Systems  Telecommunication Digital Systems  Functional Verification, Design for Test  Fault Tolerance  RFID (tags, readers, middleware) People & Infrastructure  1 st Place in I Xilinx Student Contest - SBCCI04  1 st Place in II Xilinx Student Contest - SBCCI05  Best Conceptual Design in the DATE´2005 Designers Forum  Best Paper Award s in conferences like SOCs and SBCCI  ASSESPRO-RS award for the best undergraduate project – 2009. Awards ATLAS Environment to design, generate synthetic traffic and evaluate NoCs performance Support to several mesh/torus topologies, synchronous/asynchronous communication, and other structural parameters (e.g. virtual channels, routing algorithms, flit size, etc.) Reference Paper: HERMES: an Infrastructure for Low Area Overhead Packet- switching Networks on Chip. Integration, the VLSI Journal, vol 38, no 1, pp. 69-93, Oct. 2004.  5 Researchers  11 PhD students  12 MSc students  29 Undergraduate students  50 Desktop and 6 server computers  Commercial CAD tools from Cadence, Synopsys, Mentor, Xilinx  Complete Xilinx FPGA design flow  Complete ASIC design flow  State-of-the-art ASIC technology libraries - IBM 65nm and IBM and ES2 90nm nodes  Infrastructure for cluster computing  Infrastructure for collaborative work with distributed teams (redmine, tikiwiki, svn) Open source tools  HeMPS NoC-based MPSoC and HeMPS Editor  HellFire RTOS and framework for MPSoC  Atlas NoC Designer  CloudRFID Framework  CAFES power-aware task placement for NoC-Based MPSoC HellFire Architecture HellFire System is a flexible and scalable framework for MPSoC design. Hardware Architecture:  Scalable Bus or NoC based simulation tool (N-MIPS Instruction Set Simulator)  From 1 to 128 cores can be used  Characterized instruction timing and energy consumption, based on lower level simulations  Regular NoC abstraction, used for application positioning on different cores Software Architecture:  HellFire OS: HellFire a microkernel based OS which implements most services needed for the development of parallel realtime applications.  task abstraction for multi-threaded applications  several efficient scheduling policies  scalable context switch time (min 320  s @ 100MHz)  mutual exclusion primitives  dynamic memory allocation  custom LibC  inter task communication primitives  task migration HellFire Framework: HellFire Framework - powerful interface automating OS configuration and application development  automatic configuration of OS on many-processor architecture  application mapping  performance and debug reports  graphical reports

2. Contact Ney Calazans, Professor (GAPH co-head) Fernando Moraes, Professor (GAPH co-head) Fabiano Hessel, Associate Professor (GSE head) Cesar Marcon, Associate Professor Edson Moreno, Assistant Professor Alexandre Amory, Post Doctoral Fellow {ney.calazans, fernando.moraes, fabiano.hessel, cesar.marcon, edson.moreno, alexandre.amory}@pucrs.br How to Join Send an email to one of the contacts above. MSc and PhD students applications may take place every semester. Practically all MSc and PhD students are awarded grants (CNPq/CAPES/selected enterprises). For more, check http://www.inf.pucrs.br/http://www.inf.pucrs.br/ Address Faculdade de Informática - PUCRS Av. Ipiranga, 6681 - Prédio 32 – Sala 726 90619-900 - PORTO ALEGRE - BRASIL phone: +55 51 3320 3611 FAX: +55 51 3320 3621 http://www.inf. pucrs.br/~gaph http://www.inf. pucrs.br/~gse PUCRS HERMES IP  configurable size 2D mesh network-on-chip  wormhole packet switching  no global address map – NUMA  distributed XY routing Plasma embedded processor IP  MIPS 32-bit processor architecture  32x32-bit register file  MIPS-I instruction set Memory IP  16KB or 32KB per processor, dual port Operating System  Small proprietary microkernel  Support to multitask and message passing CAD for automatic system generation  HeMPS Editor (automatic MPSoC generator)  Creates RTL and simulation models Reference Paper  Carara, E.; Oliveira, R.; Calazans, N.; Moraes, F. HeMPS - A Framework for NoC-Based MPSoC Generation. ISCAS 2009. pp. 1345-1348. HeMPS MPSoC