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Network based System on Chip Students: Medvedev Alexey Shimon Ofir Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006.

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Presentation on theme: "Network based System on Chip Students: Medvedev Alexey Shimon Ofir Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006."— Presentation transcript:

1 Network based System on Chip Students: Medvedev Alexey Shimon Ofir Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006

2 Problem In modern high-speed systems that contain a lot of components traffic is a major problem. Components are interacting with each other using a bus.

3 Problem

4 This architecture has certain disadvantages:  low speed,  allows to connect only two components at a given time,  no parallel access,  unconfigurable.

5 Solution

6 On-chip packet-switched networks have been proposed as a solution for the problem of global interconnect in deep sub-micron VLSI Systems on Chip (SoC).

7 Solution Networks on Chip (NoC) can address and contain major physical issues such as  parallelization,  noise,  error correction,  speed optimization. NoC can also improve design productivity by supporting modularity and reuse of complex cores, thus enabling a higher level of abstraction in architectural modeling of future systems.

8 Project Goals Understand NoC protocol Implement NoC and NoC router using a FPGA system Implement Flow Control Unit and Hot-Spot Controller

9 Example: FCU Hot-Spot Data High Priority Data Low Priority Data R Transmissio n Request Data

10 NoC Router Switch Buffers (with Virtual Channels and wormhole data transfer)

11 Virtual Channels & Wormholes Wormhole means that the data is transmitted in a constant flow rather than in packets. Using virtual channel we can manage to transmit more than one data stream through a router.

12 HW & SW used Xilinx ML-310 Evaluation board with VirtexII Pro FPGA HDL designer ModelSim 6.1 Xilinx EDK 6.3i

13 Project Schedule Week 1: Get familiar with the Virtex II pro FPGA Week 2: Get familiar with the PowerPC 405 processor Week 3-4: Studying the VHDL programming language. Week 5: Get familiar with the FPGA design process. Week 6: Studying the EDK software for developing SoC

14 Week 7: Writing a simple application. Week 8-9: Developing NoC protocol Week 10-12: Implementing a simple router for NoC. Week 13-14: Implementing a basic NoC. Project Schedule

15 Project Schedule (second semester) Implementing a Source Flow Control Unit Implementing a Hot-Spot Flow Control Unit (Scheduler) for bandwidth - consuming components.

16 The End


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