1. 1 CS 352 Introduction to Logic Design Lecture 4 Ahmed Ezzat Multi-level Gate Circuits and Combinational Circuit Design Ch-7 + Ch-8

2. CS-352Ahmed Ezzat 2 Outline Multi-level Gate Circuits NAND and NOR Gates Design of 2-level Using NAND and NOR-Gates Design of Multi-level NAND and NOR-Gate Circuits Circuit Conversion Using Alternative Gate Symbols Design of two-level, Multiple-Output Circuits Multiple-Output NAND and NOR Circuits Review of Combinational Circuit Design Design of Circuits with Limited Gate Fan-In Gate Delays and Timing Diagrams Hazards in Combinational Logic Simulation and Testing of Logic Circuits

3. CS-352Ahmed Ezzat 3 Multi-level Gate Circuits (1) Maximum number of gates cascaded in series between a network input and output is the number of LEVELS of gates. Any function in sum-of-products form or product-of-sums form corresponds directly to a two-level circuit. We assume that all variables and their complement are available as circuit inputs (as a result. inverters are generally not counted). Number of levels can be increased by factoring the sum-of- products expression or by multiplying out some of the terms in the product of sums.

4. CS-352Ahmed Ezzat 4 Multi-level Gate Circuits (2) Number of levels typically is limited by allowed gate delays.

5. CS-352Ahmed Ezzat 5 Multi-level Gate Circuits (3) Example: find optimal circuit of AND and OR gates for: F(a,b,c,d) = Σ m(1,5,6,10,13,14) We will realize this Karnaugh map using 2-levels with an output as AND or OR gate We will realize this Karnaugh map using 3-levels with an output as AND or OR gate

6. CS-352Ahmed Ezzat 6 Multi-level Gate Circuits (4) Output OR Gate: – 2-levels Gates: 3-levels Gates: F = a’c’d + bc'd + bcd’ + acd’F = c’d(a’ + b) + cd’(a + b)

7. CS-352Ahmed Ezzat 7 Multi-level Gate Circuits (5) Output AND Gate: – 2-levels Gates: 3-levels Gates: F’ = c’d’ + ab’c’ + cd + a’b’c F = (c + d)(a’ + b + c)(c’ + d’)(a + b + c’) Using (X + Y)(X + Z) = X + YZ F = (c + a’d + bd)(c’ + ad’ + bd’)

8. CS-352Ahmed Ezzat 8 Multi-level Gate Circuits (6) The best 2-levels solution had an AND gate at the output, and the best 3-levels solution has an OR gate at the output. In order to find the minimum # of gates, you must find both circuits with both AND and OR gate output!

9. CS-352Ahmed Ezzat 9 NAND and NOR Gates (1) NAND and NOR gates are more popular than AND and OR gate as they are faster and use fewer components. A set of logic operations is functionally complete if its boolean function can be expressed in terms of AND, OR and NOT. F = (X 1 X 2 ….X n )’F = (X 1 + X 2 + ….+ X n )’ = X 1 ’X 2 ’ ….. X n ’

10. CS-352Ahmed Ezzat 10 NAND and NOR Gates (2) Procedure to determine if a given set of gates are functionally complete? – Write out a minimum sun-of-products expression for the function realized by each gate. – If no complement appears in any of these expressions, then NOT cannot be realized, and the set is not functionally complete. – If complement appears in one of the expressions, the NOT can generally be realized – Next attempt to realize AND or OR, keeping in mind that NOT is now available – Once AND or OR has been realized, the other one can always be realized using DeMorgan’s law, e.g. XY = (X’ + Y’)’

11. CS-352Ahmed Ezzat 11 Design of 2-level NAND and NOR-Gate Circuits (1) Figure 7-11a represents the following forms: – AND-OR – NAND-NAND – OR-NAND – NOR-OR

12. CS-352Ahmed Ezzat 12 Design of 2-level NAND and NOR-Gate Circuits (2) Figure 7-11b represents the following forms: – OR-AND – NOR-NOR – AND-NOR – NAND-AND

13. CS-352Ahmed Ezzat 13 Design of Multi-level NAND and NOR-Gate Circuits (1) Simplify the switching function to be realized. Design a multi-level circuit of AND and OR gates. The output gate must be an OR gate. Number the levels starting with the output gate as level-1. Replace all gates with NAND gates, leaving all interconnections between gates unchanged. Leave the inputs to levels 2, 4, 6… unchanged. Invert any literals that appear as input to levels 1, 3, 5, …

14. CS-352Ahmed Ezzat 14 Design of Multi-level NAND and NOR-Gate Circuits (2)

15. CS-352Ahmed Ezzat 15 Circuit Conversion Using Alternative Gate Symbols (1) Alternate symbols for gates can be used to facilitate converting circuits from one form to another. Alternative Gate Symbols:

16. CS-352Ahmed Ezzat 16 Circuit Conversion Using Alternative Gate Symbols (2) Convert NAND circuit to AND-OR circuit:

17. CS-352Ahmed Ezzat 17 Circuit Conversion Using Alternative Gate Symbols (3) Convert AND-OR circuit to NOR circuit:

18. CS-352Ahmed Ezzat 18 Design of 2-level, Multiple-Output Circuits (1) Design a circuit with 4-inputs and 3-outputs which realizes the functions: – F 1 (A,B,C,D) = Σ m(11, 12, 13, 14, 15) – F 2 (A,B,C,D) = Σ m(3, 7, 11, 12, 13, 15) – F 3 (A,B,C.D) = Σ m(3, 7, 12, 13, 14, 15)

19. CS-352Ahmed Ezzat 19 Saving in Gates, however multiple output realization is not a minimum sum- of-products, i.e., F2 = ABC’ + A’CD + ACD! Design of 2-level, Multiple-Output Circuits (2)

20. CS-352Ahmed Ezzat 20 When designing multiple-output circuits, we should minimize the total number of gates. If several solutions require the same number of gates,, then we should select the solution with minimum number of gate inputs. First, plot maps for F 1, F 2, and F 3 where each is minimized separately. Design of 2-level, Multiple-Output Circuits (3)

21. CS-352Ahmed Ezzat 21 Separate optimization (10 gates + 25 gate inputs): – F 1 = bd + b’c + ab’ – F 2 = c + a’bd – F 3 = bc + ab’c’ + {abd or ac’d) Multiple Output Optimization (8 gates + 22 gate inputs): – F 1 = a’bd + abd + ab’c’ + b’c – F 2 = c + a’bd – F 3 = bc + ab’c’ + abd We exchanged bd in F 1 by (a’bd + abd)  not minimum sum-of-products Terms in common between two functions are underlined Design of 2-level, Multiple-Output Circuits (4)

22. CS-352Ahmed Ezzat 22 Multiple-Output NAND and NOR Circuits Procedure discussed for converting NAND to AND-OR and AND-OR to NOR with single output are applicable to multiple outputs: – If output is OR, conversion to NAND is possible – If output is AND, conversion to NOR is possible F 1 = [(a + b’)c + d](e’ + f) F 2 = [(a + b’)c + g’](e’ + f)h

23. CS-352Ahmed Ezzat 23 Review of Combinational Circuit Design (1) Write truth table including don’t care for never occurring input combination. Derive simplified algebraic using Karnaugh map, Quine-McCluskey method, or others. In some cases (large number of variables), go directly to algebraic equation  simplified algebraically  put into proper form depending on type of gates to be used in realizing the circuit. Number of levels in a gate circuit = max # of gates signal has to go through between input and output terminals. Minimum sum-of-products (or product-of-sums) leads to 2-level gate circuit. With multiple outputs, if each function is minimized separately, it does not lead to a minimum multiple-output circuit.

24. CS-352Ahmed Ezzat 24 Review of Combinational Circuit Design (2) Common terms in multiple-output circuit can be found from Karnaugh map. Minimum 2-level AND-OR, NAND-NAND, OR-NAND, and NOR-OR circuits can be realized using minimum sum-of-products as a starting point. Minimum 2-level OR-AND, NOR-NOR, AND-NOR, and NAND-AND circuits can be realized using minimum product-of-sums as a starting point. Design of multi-level, multiple-outputs NAND gate circuits is easily done by first designing a circuit of AND and OR gates (sum-of- products followed by factoring) – typically an OR gate for each output. Design of multi-level, multiple-outputs NOR gate circuits is easily done by first designing a circuit of AND and OR gates (sum-of- products for the complement of the output function  factoring  complement) - typically an AND gate for each output.

25. CS-352Ahmed Ezzat 25 Design of Circuits with Limited Gate Fan-In (1) Sometimes, number of inputs (fan-in) on each gate is limited (our 2-level realization requires more), then factoring the logic expression to obtain a multi-level realization is necessary. Example: Realize F(a,b,c,d) = Σ m(0,3,4,5,8,9,10,14,15) using 3-input gates! F’ = a’b’c’d + ab’cd + abc’ + a’bc + a’cd’ 2-level realization requires 2 4-input gates + 1 5-input gate! ab cd 00 1 1 1100 01 101 10 010

26. CS-352Ahmed Ezzat 26 Design of Circuits with Limited Gate Fan-In (2) Instead, F’ expression is factored to reduce the maximum number of gate inputs  then it is complemented F’ = b’d(a’c’ + ac) + a’c(b +d’) + abc’ F = [b + d’ + (a + c)(a’ + c’)][a + c’ +b’d][a’ + b’ + c]  NOR gate circuit

27. CS-352Ahmed Ezzat 27 Design of Circuits with Limited Gate Fan-In (3) Realize the following multiple output function using 2-input NAND gates! F 1 = b’c’ + ab’ + a’bF 2 = b’c’ + bc + a’bF 3 = a’b’c’ + ab + bc’

28. CS-352Ahmed Ezzat 28 Design of Circuits with Limited Gate Fan-In (4) Each function requires 3-input OR gate  factor to reduce # of inputs: F 1 = b’(a + c’) + a’bF 2 = (b’ + c)(b + c’) + a’bF 3 = a’b’c + b(a + c’) = a’(b + c’)’ + b(a + c’)

29. CS-352Ahmed Ezzat 29 Gate Delays and Timing Diagrams (1) Output of a gate changes after delay from the input changes

30. CS-352Ahmed Ezzat 30 Gate Delays and Timing Diagrams (2) A circuit with two gates:

31. CS-352Ahmed Ezzat 31 Hazards in Combinational Logic When transient occur with different paths from input to output with different propagation delays, the response to change in an input can be as follows: – The circuit may momentarily go to 0 when it should remain constant 1  static 1-hazard. – The circuit may momentarily go to 1 when it should remain constant 0  static 0-hazard. – If the circuit is supposed to change from 0 to 1 (or 1 to 0), and the output change three or more times, we say the circuit has a dynamic hazard. Circuits can be modified to remove hazard.

32. CS-352Ahmed Ezzat 32 Simulation and Testing of Logic Circuits (1) An important aspect of logic design is to validate that the final design is correct, and debugging the design if necessary. Circuits can be tested after building them or by simulating them on a computer. Simulation is generally easier and cheaper. Simulation helps in: – Verify that the design is logically correct – Verify that the timing of the logic circuit is correct – Simulating faulty components in the circuit to help building tests for the circuit

33. CS-352Ahmed Ezzat 33 Simulation and Testing of Logic Circuits (2) Typical simulation screen: – Some times value of a gate input may be unknown  X – Value Z represent an open circuit (high impedance) – Probe indicates the value of a gate output

34. CS-352Ahmed Ezzat 34