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Unit 8 Combinational Circuit Design and Simulation Using Gates Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

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22004/03/11Fundamentals of Logic Design Contents 8.1Review of Combinational Circuit Design 8.2Design Circuits with Limited Gate Fan-In 8.3Gate Delays and Timing Diagrams 8.4Hazards in Combinational Logic 8.5Simulation and Testing of Logic Circuits

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32004/03/11Fundamentals of Logic Design Combinational v.s. Sequential Combinational circuit Output values depend only on the present value of the inputs (not on the past values) Output values depend only on the present value of the inputs (not on the past values) Sequential circuit Output values depend on both present and past input values Output values depend on both present and past input values Composed of Composed of A combinational circuit Added memory elements

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42004/03/11Fundamentals of Logic Design Combinational Circuit Design First step Set up a truth table Set up a truth table n input variables -> 2 n rows Don’t care condition Don’t care condition A given combination never occurs Next step Derive simplified expression Derive simplified expression Karnaugh maps Quine-McCluskey

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52004/03/11Fundamentals of Logic Design Combinational Circuit Design Third step Manipulate simplified expressions into proper form Manipulate simplified expressions into proper form Depending on the type of gates to be used in realizing the circuit Factoring or multiplying out Levels Levels Gates Gates Gate inputs Gate inputs

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62004/03/11Fundamentals of Logic Design Combinational Circuit Design Minimum sum-of-products AND-OR, NAND-NAND, OR-NAND, NOR-OR AND-OR, NAND-NAND, OR-NAND, NOR-OR

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72004/03/11Fundamentals of Logic Design Combinational Circuit Design Minimum product-of-sums OR-AND, NOR-NOR, AND-NOR, NAND-AND OR-AND, NOR-NOR, AND-NOR, NAND-AND

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82004/03/11Fundamentals of Logic Design Contents 8.1Review of Combinational Circuit Design 8.2Design Circuits with Limited Gate Fan-In 8.3Gate Delays and Timing Diagrams 8.4Hazards in Combinational Logic 8.5Simulation and Testing of Logic Circuits

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92004/03/11Fundamentals of Logic Design Limited Gate Fan-in The maximum number of inputs on each gate (or the fan-in) is limited. Factoring maybe necessary Factoring maybe necessary

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102004/03/11Fundamentals of Logic Design Example Realize f(a,b,c,d) = ∑m(0, 3, 4, 5, 8, 9, 10, 14, 15) using 3-input NOR gates.

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112004/03/11Fundamentals of Logic Design Karnaugh Map 1101 0101 1010 0011 00 01 11 10 ab cd 00 01 11 1011010101 1010 0011 ab cd 00 01 11 10

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122004/03/11Fundamentals of Logic Design Karnaugh Map f ’ = a’b’c’d + ab’cd + abc’ + a’bc + a’cd’ 1101 0101 1010 0011 00 01 11 10 ab cd 00 01 11 10

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132004/03/11Fundamentals of Logic Design Resulting NOR-gate circuit f ’ = a’b’c’d + ab’cd + abc’ + a’bc + a’cd’ = b’d (a’c’ + ac) + a’c (b + d’) + abc’ f = [b+d’+(a+c)(a’+c’)] [a+c’+b’d] [a’+b’+c]

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142004/03/11Fundamentals of Logic Design Example Realize the functions, using only 2-input NAND gates and inverters. f 1 = ∑m(0, 2, 3, 4, 5) f 1 = ∑m(0, 2, 3, 4, 5) f 2 = ∑m(0, 2, 3, 4, 7) f 2 = ∑m(0, 2, 3, 4, 7) f 3 = ∑m(1, 2, 6, 7) f 3 = ∑m(1, 2, 6, 7)

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152004/03/11Fundamentals of Logic Design Karnaugh Map f 1 = b’c’ + ab’ + a’b f 1 = b’c’ + ab’ + a’b f 2 = b’c’ + bc + a’b f 2 = b’c’ + bc + a’b f 3 = a’b’c + ab + bc’ f 3 = a’b’c + ab + bc’

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162004/03/11Fundamentals of Logic Design Factoring To introduce common terms wherever possible f 1 = b’c’ + ab’ + a’b = b’(a+c’) + a’b f 1 = b’c’ + ab’ + a’b = b’(a+c’) + a’b f 2 = b’c’ + bc + a’b = b(a’+c) + b’c’ or (b’+c)(b+c’) + a’b f 2 = b’c’ + bc + a’b = b(a’+c) + b’c’ or (b’+c)(b+c’) + a’b f 3 = a’b’c + ab + bc’ = a’b’c + b(a+c’) f 3 = a’b’c + ab + bc’ = a’b’c + b(a+c’) Eliminating 3-input gate from f 3 a’b’c = a’(b’c) = a’(b+c’)’ a’b’c = a’(b’c) = a’(b+c’)’

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172004/03/11Fundamentals of Logic Design Realization

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