1. 3D Technology and SRAM Simulation Advisor : Yi-Chang Lu Student : Chun-Yen Lin Graduate Institute of Electronics Engineering National Taiwan University

2. Graduate Institute of Electronics Engineering, National Taiwan University WHY 3D ? Moore’s Law Interconnection Delay IntegrationArea chip1 chip2 chip3 chip4 Chip2 Chip3 Chip4 Chip1 Ref: [1]

3. 3D Technology Graduate Institute of Electronics Engineering, National Taiwan University Package stacking Ref: [3] [5]

4. Graduate Institute of Electronics Engineering, National Taiwan University Wafer stacking 3D Technology Ref: [6]

5. Graduate Institute of Electronics Engineering, National Taiwan University Chip stacking Ref: [2] [7] 3D Technology

6. Graduate Institute of Electronics Engineering, National Taiwan University Device stack 3D Technology Ref: [4]

7. Stacked SRAM Graduate Institute of Electronics Engineering, National Taiwan University

8. Stacked SRAM Graduate Institute of Electronics Engineering, National Taiwan University X-decoder IN Y-decoder SA Memory Array Layer1 Layer2 Y-selector

9. 2D 3D and 2D and 3D 6T SRAM Monte Carlo Simulation Waveform 500MHz 833MHz BL Discharged Output Output

10. TSV (Through Silicon Via) Graduate Institute of Electronics Engineering, National Taiwan University 0% -5% -10% 5% 10% Ref: [2]

11. TSV (Through Silicon Via) Graduate Institute of Electronics Engineering, National Taiwan University Diameter Layer1 Layer2 Layer1 Layer2 Layer3 Layer1 Layer2 Layer3 Layer4

12. TSV (Through Silicon Via) Graduate Institute of Electronics Engineering, National Taiwan University Inserted count TSV Pitch

13. 2D and 3D SRAM Monte Carlo Simulation Results SRAM Size:256×8=2K / TSV variation Frequency Success count Graduate Institute of Electronics Engineering, National Taiwan University

14. 2D and 3D 6T SRAM Monte Carlo Simulation results (500MHz) / s RAM Size:256×8=2K / 1,2,3 and 4 layers VDD1.8V1.6V1.4V1.2V 3D_4layers200 19179 3D_3layers200 19179 3D_2layers200 19074 2D20019214812 Success count VDD Graduate Institute of Electronics Engineering, National Taiwan University

15. VDD1.8V1.6V1.4V1.2V 3D_27 ° C 200 19074 2D_27°C20019214812 3D_87°C20019615528 2D_87°C18715651 0 3D_147°C19115988 0 2D_147°C148107 0 0 Success count VDD Graduate Institute of Electronics Engineering, National Taiwan University 2D and 3D 6T SRAM Monte Carlo Simulation results (500MHz) / s RAM Size:256×8=2K / Temperature

16. Reference Graduate Institute of Electronics Engineering, National Taiwan University [1] Robert S. Patti Member IEEE “Three-Dimensional Integrated Circuit and the Future of System-on-Chip Design” Proceedings of IEEE, vol. 94, No. 6, June 2006. [2] Mitsumasa Koyanagi, et al. “Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections” IEEE, Transactions on Electron Devices, Vol.53, No.11, Nov 2006. [3]Moody Dreiza, Akito Yoshida et al. “High Density PoP(package on package) and Package Stacking Development” [4]Jung, et al “Highly Cost Effective and High Performance 65nm S 3 (Stacked Single-Crystal Si) SRAM Technology with 25F 2, 0.16um 2 Cell and Doubly Stacked SSTFT Cell Transistors for Ultra High Density and High Speed Applications” Symposium on VLSI Technology Digest of Technical Papers, pp.220-221, June, 2005. [5] John U. Knickerbocker, et al “3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias” IEEE Journal of Solid-State Circuit, Vol. 41, No. 8, Aug 2006. [6] James A. Burns, et al “A Wafer-Scale 3-D Circuit Integration Technology” IEEE Transactions on Electron Devices, Vol.53, No.10, Oct 2006. [7]Fukushima et al., “New three-dimensional integration technology using self-assembly technique,” IEEE International Electron Devices Meeting Technical Digest, pp 348-351, Dec 2005.