1. Hao-Hsuan, Liu IEE5011 –Autumn 2013 Memory Systems 3D DRAM using TSV technology Hao-Hsuan, Liu Department of Electronics Engineering National Chiao Tung University h1616161@Hotmail.com

2. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Outline Introduction 3D Technology-TSV 3D Processor-DRAM Integration Impacts of TSV in 3D DRAM system Conclusion Reference 2

3. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Introduction-Why we use 3D DRAM? Speed - Memory wall -The growing disparity of speed between CPU and memory Area Power Cost 3

4. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D technology (a) 3D packaging technology - Wire bonding, flip-chip bonding, and thinned die to die bonding - Very low interconnect density (b) Transistor build-up 3D technology - High vertical interconnect density - Temperature constraint - Tend to degrade the performance 4

5. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D technology (c) Monolithic wafer-level 3D technology - Wafer alignment - Bonding - Thinning - Inter-wafer interconnection - Realized by TSV can have very high density 5

6. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Through-Silicon Via (TSV) Device Process: FEOL(Front-End OF Line)-> BEOL(Back)-> Bonding Via-First: - Before FEOL Via-Middle: - After FEOL, before BEOL Via-Last: - (1) After BEOL - (2) After Bonding[21] 6

7. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Through-Silicon Via (TSV) 7 TSV process flow

8. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Through-Silicon Via (TSV) Via-First - Vias are made before CMOS 8

9. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Through-Silicon Via (TSV) Via-Middle - Vias are made between CMOS and BEOL 9

10. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Through-Silicon Via (TSV) Via-Last( After BEOL before Bonding) - Vias are made after BEOL 10

11. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Through-Silicon Via (TSV) Via-Last( After Bonding) - Vias are made after Bonding 11

12. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D DRAM Integration Processor consume more energy and generate more heat Stacking a single processor with multiple DRAM dies Processor locates closest to the heat sink 12

13. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D DRAM Integration 3D Process-DRAM integrated system architecture 13

14. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D DRAM Integration Clearly, through-DRAM TSVs will - Impact the 3D DRAM design - Degrade DRAM storage capacity - Power consumption How to design the TSVs placement? 14

15. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D DRAM Integration Proposed design to allocate through-DRAM TSVs 15

16. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D DRAM Integration Signal TSVs - minimum allowable TSV size - Tend to occupy a very small area - At the center of DRAM dies Power TSVs - Much bigger impact and design trade-offs - Power consumption overhead Reduce the resistance of power TSVs Increase size 16

17. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu 3D DRAM Integration Propose to arrange a regular power TSV network around those DRAM sub-arrays 17

18. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Impacts of TSV in 3D DRAM system Impacts of the size of each power TSV 18

19. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Impacts of TSV in 3D DRAM system Impacts of the DRAM Sub-array Size 19

20. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Impacts of TSV in 3D DRAM system Impacts of the DRAM substrate thickness 20

21. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Impacts of TSV in 3D DRAM system Impacts of the contact resistance 21

22. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Conclusion 3D DRAM integration drive innovational changes in performance, power, and cost. Through-silicon-via(TSV) is widely used in the 3D technology, and its parameter will impact the performance and power in 3D system A simple method to allocate power and signal TSVs lead to simply consider the trade-offs. 22

23. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Reference [1]P. Kogge, et al., “Exascale computing study: Technology challenges in achieving exascale systems,” 2008. [2]F. Fishburn, et al., “A 78nm 6F2 DRAM Technology for Multigigabit Densities,” in VLSIT, 2004. [3]M. A. Horowitz, “Timing Models for MOS Circuits,” Stanford University,Tech. Rep., 1984. [4]J. Kim, et al., “A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4x128 I/Os Using TSV-Based Stacking,” in ISSCC, 2011. [5]K-H. Kyung, et al., “A 800Mb/s/pin 2Gb DDR2 SDRAM using an 80nm Triple Metal Technology,” in ISSCC, 2005, pp. 468–469. [6]M. Nakamura, et al., “A 29ns 64Mb DRAM with Hierarchical ArrayArchitecture,” in ISSCC. IEEE, 1995, pp. 246–247. [7]G. Katti, et al., “Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs,” IEEE Trans. on Electron Devices, no. 1, pp. 256–262, January 2010. 23

24. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Reference [8]T.A.C.M. Claasen, “An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology,” Proceedings of the IEEE, vol. 94, pp. 1121–1137, June 2006. [9]J.-Q. Lu, T.S. Cale, and R.J. Gutmann, “Wafer-level three-dimensional hyper-integration technology using dielectric adhesive wafer bonding,” Materials for Information Technology: Devices, Interconnects and Packaging (Eds. E. Zschech, C. Whelan, T. Mikolajick), pp. 386–397, Springer- Verlag (London) Ltd, August 2005. [10]R.S. Patti, “Three-dimensional integrated circuits and the future of systemon-chip designs,” Proceedings of the IEEE, vol. 94, pp. 1214–1224, June2006. [11]K. Itoh, VLSI Memory Chip Design, Springer, 2001. [12]G. H. Loh, “3D-Stacked Memory Architectures for Multi-Core Processors,” in Proceedings of the 35th ACM/IEEE International Symposium on Computer Architecture, 2008. [13]G. H. Loh, Y. Xie, and B. Black, “Processor Design in 3D Die-Stacking Technologies,” IEEE Micro, vol. 27, pp. 31–48, May-June 2007. [14]Y.-F. Tsai, F. Wang, Y. Xie, N. Vijaykrishnan, and M. J. Irwin, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 444– 455, April 2008. 24

25. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Reference [15]S. Thoziyoor, J. Ahn, M. Monchiero, J. B. Brockman, and N. P. Jouppi, “A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies,” in ISCA, 2008. [16]T. Vogelsang, “Understanding the Energy Consumption of Dynamic Random Access Memories,” in MICRO, 2010, pp. 363–374. [17]U. Kang, et al., “8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology,” JSSC, vol. 45, no. 1, pp. 111–119, 2010 [18]J. T. Pawlowski, “Hybrid Memory Cube (HMC),” in Proceedings of Hot Chips 23, 2011. [19]Y.-F. Tsai, Y. Xie, V. Narayanan, and M. J. Irwin, “Three-Dimensional Cache Design Exploration Using 3D Cacti,” in ICCD, 2005 [20]I. Savidis and E. Friedman, “Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance,” IEEE Trans. on Electron Devices, vol. 56, no. 9, September 2009. [21]R. Weerasekera, et al., “Compact Modelling of Through-Silicon Vias (TSVs) in Three- Dimensional (3-D) Integrated Circuits,” in 3DIC, 2009. 25

26. NCTU IEE5011 Memory Systems 2013Hao-Hsuan, Liu Thanks for your attention! 26