1. Pi-Feng Chiu, Pengpeng Lu, Zeying Xin EECS, UC Berkeley 05/06/2013
Differential 2R Crosspoint RRAM for Memory system in Mobile Electronics with Zero Standby Current
Hi everyone, I’m Pi-Feng and my partners are pengpeng and zeying.
I slightly change the title of the project to fit the content better.
So the idea is to use RRAM as cache in the chip of your cell phone.
But I’ll put most emphasis on how to build to RRAM chip instead of the architectural stuff
You may ask what is RRAM? We’ll talk about it later.
Pi-Feng Chiu, Pengpeng Lu, Zeying Xin EECS, UC Berkeley
05/06/2013

2. Outline Introduction Issues of Crosspoint Array
Memory Hierarchy
RRAM switching mechanism
Issues of Crosspoint Array
Proposed Differential 2R cell
Cell Characteristics
Differential 2R cell and array design
Circuit Implementation
Divided WL and Sense-before
Simulation Results
Comparison
Conclusion
This is the outline of today’s presentation.
I’ll briefly talk about the memory hiercarchy and what is RRAM
The current problem of RRAM
Our proposed scheme to solve the problem
How we build the circuit and the simulation result
Finally, we’ll compare several metrics between SRAM and RRAM.
And I’ll conclude this talk

3. Permanent Storage Hard Disk Drive, Solid State Drive
Memory Hierarchy
CPU Register
Cache L1 L2
Main Memory (DRAM)
Permanent Storage Hard Disk Drive, Solid State Drive
Leakage issue
Perfect Memory:
Nonvolatile
High speed
Small Area
Low power
High Endurance
High memory density
High speed
I believe everyone knows this pyramid of memory hierarchy. It is a tradeoff between memory density and speed.
The high-speed memory usually needs larger area. Therefore, memory hierarchy is built to create an illusion of fast and large memory.
Also, the leakage issue of SRAM get more critical as technology scaling down. NVM would not have standby leakage, but it’s slow.
So If there were one perfect nonvolatile memory with high speed, small area and high endurance, it would crash the existent memory hierarchy and form an one-memory system.
Unfortunately, there is no such a perfect memory so far. Although the operation speed of RRAM is not as fast as that of L1 cache
But what we know is there are many exciting researches of emerging nvm in recent years, which may get channce to change this system in future
Slow

4. RRAM switching mechanism
RRAM: Resistive Random Access Memory
Sandwiched cell structure
SET: Switching to Low Resistance State (LRS)
RESET: Switching to High Resistance State (HRS)
So one of the most promising candidates is RRAM, RRAM stands for resistive random acess memory
There are many different recipes for resistive storage materials in the ongoing researches.
Typically, the cell structure is like a tiny sandwich with two metal electrodes on top and bottom and metal-oxide in the middle.
For example, this figure shows the middle material ,made of titanium dioxide (TiO2)
It forms two layers, the bottom one is electrically insulting TiO2
And the upper one the conductive with its positive charged oxygen vacancies.
RRAM cell is a device whose resistance depends on the magnitude and polarity of the voltage applied to it and the length of time that voltage has been applied. Fi
. A positive voltage on the cell repels the (positive) oxygen to lower layer, the conductive layer is thicker, therfore the resistance is smaller. It’s called SET operation
On the other hand, in the RESET operation, the negative attracts the positively charged oxygen vacancies2. The insulating layer gets thicker, and the resistance is The resistance

5. Crosspoint Issues 1T1R  Crosspoint structure Leakage issues:
Write – write energy efficiency
Read – read margin
Write Disturbance
n: BL number, m: WL number
(a)
Conventional, the RRAM cell is composes by one transistor and one resistor.
However, to drive enough current, the transistor needs to be large therefore dominate the cell area
So people move to the crosspoint structure, the device is sanwidched between WL and BL
However, without the access transistor, there are tons of problems need to be solve
First, leakage current. We don’t have isolation for the unselected cells. Which would lead to low write energy efficiecy and low read margin
Second, Write disturnace, we need to prevent the voltage drop on unslected cells is not large enough to switch it.
Therefore we need to bias the unselected BL. There are four scheme, H means provide half of the write voltage, F means Floating
The equivalent circuit for calculate leakge current is shown as the figure and the equation
By taking n=m=16, we can find that FWHB has the lowest leakage current with stable operaiton.
(b)
(c)

6. Cell Characteristics Tradeoffs RLow vs. write energy
Write time vs. Write voltage
Write energy vs. Write voltage
Read margin vs. Rlow
Sensitivity to Write time
To start to design to RRAM crosspoint circiut, we need to determine some parameters like low reistance state, high resistance state, write voltage, read voltage and write time
To get the information, we simulated the Verilog-A cell model by eldo.
And we found some tradeoffs of the design parameters

7. Differential 2R cell WLa[1] WLb[1] WLa[0] WLb[0] BL0 BL1 BL2 Ra Rb+ -
In read operation,
WLa=Vread, WLb=0 Voltage-sensing VBL
VBL=Vread*Rb/(Ra+Rb)
Write-1
Write-0 Ra
SET
RESET Rb WL
Vwrite BL
To solve the leakage issue when reading cells in crosspoint array, we proposed the differential 2R crosspoint structure, as shown in Fig. 6(a). In this scheme, two resistive devices with opposite resistance states together represent 1-bit datum. To store a 1, Ra is written to low resistance state (LRS) and Rb is written to high resistance state (HRS); to store a 0, Ra is in HRS and Rb is in LRS. Instead of sensing the current flowing through the cell, the state of a differential 2R cell is determined simply by the voltage divider of Ra and Rb. In read operation, the BL voltage would be Vread*Rb/(Ra+Rb) by applying Vread across Ra and Rb. The BL is then connected to a simple StrongARM sense amplifier with a reference voltage of Vread/2. Therefore, the read operation is immune to the leakage current flowing in from neighbor BLs and greatly increases the read margin without limiting the block size. Moreover, the differential 2R cell contains both RH and RL, which solves the data pattern issue and suppresses the leakage consumption in read operation.
Operate voltage
write
Assumption: VSET=VRESET=Vwrite

8. Divided WL
To constrain overall write current to 100~200uA, WL length need to be set to 4-cell wide
Divided WL: decouple local WLs and connect to global WL by switches.
Tradeoff between leakage current and area penalty
GWLb
BEOL process enables stack ability
GWLa
The cross-sectional view of the array is shown in this figure We
Thanks to the stack ability of RRAM, the differential 2R cell can be constructed between different metal layers without much area penalty. Since Ra and Rb have opposite electrodes connected to WLa and WLb, we can SET one device and RESET another at the same time by applying the same voltage on WLa and WLb. … Ra
LWLa Rb
LWLb BL
SWa
SWb

9. Sense-before-Write I(cell)
Resistance value drops if a SET pulse repeatedly access to the cell.
Solution:
Lowest resistance value
Targeted resistance value
I(cell)
DIN
If DIN= DOUT ?
Write?
Read
Yes
Pass
DOUT No
Write

10. Block diagram

11. Vref Write-0 to cell01 Write-1 to cell11 R1 R0 Write operation
WLa[0]
WLb[0]
WLa[1]
WLb[1]
BL[1]
DOUT
I(cell01b)
I(cell01a)
Write-0 to cell01
~Vwrite/2
~Vwrite
SET
RESET
Write-1 to cell11 R1 R0
Vref
Write operation
Read operation

12. Features

13. Comparison Differential 2R RRAM SRAM Performance 500MHz > 1GHz
Active Power
Large (DC current)
Small (Static Logic)
Standby Leakage
570pJ/cell
Area
0.04 um2 (*)
0.1 um2 (22nm)
Endurance
~108
>1014
*: assume metal width and space are 50nm, area = (0.05*4)2
Fit for L2/L3 cache in mobile electronics to save battery life

14. Conclusion ? Differential 2R crosspoint RRAM design
64KB RRAM circuit
Divided WL and Sense-before-Write approach
28/32nm PTM, RRAM cell model, Eldo simulator
Crosspoint RRAM  Cache?
Area: yes
Power: depending on application
Endurance
Future Work:
Cell characterization
Leakage reduction, Cell distribution
I’m concluding this talk,
We accomplish a 64KB differential 2R crosspoint RRAM cicuit with divided WL and sense-before-wirte technique
It is simulated by Eldo with 28/32 PTM and RRAM cell model
So it is possible that crosspoint RRAM can substitue SRAM as a cache
In terms of area
Power
However, endurance is the biggest concern for frequent accessed memory
For future work ?

15. Thanks!

16. Reference ITRS Roadmap (http://www.itri.net)
Yan Li, et al., “128Gb 3b/cell NAND Flash Memory in 19nm Technology with 18MB/s Write Rate and 400Mb/s Toggle Mode,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp
T. Takashima, et al., “A 100MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 3, March 2011.
T. Shigibayashi, et al., “A 16-Mb Toggle MRAM With Burst Modes,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 11, Nov
D. C. Ralph and M. D. Stiles, “Spin Transfer Torques,” Journal of Magnetism and Magnetic Materials, vol. 320, issue 7, pp , April 2008.
R. E. Simpson, et al., “Toward the Ultimate Limit of Phase Change in Ge2Sb2Te5,” Nano Letter, pp , 2010.
Elaine Ou and S. Simon Wong, “Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp , Sep
R. Stanley Williams, “How we found the missing memristor,” IEEE Spectrum, vol. 45, no. 12, pp , 2008.
A. Kawahara, et al., “An 8Mb Multi-Layered Cross-Point ReRAM Macro With 443MB/s Write Throughput,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, January 2013.
D. Niu, C. Xu, N. Muralimanohar, N. P. Jouppi, Y. Xie, “Design Trade-Offs for High Density Cross-Point Resistive Memory,” ISLPED, 2012, pp
M. Yoshimoto, et al., “A Divided Word-line Structure in the Static SRAM and Its Application to a 64K Full CMOS RAM” IEEE Journal of Solid-State Circuits, Vol. 18, No. 5, Oct
P. Packan, et al., “High Performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors,” in Int. Electron Devices Meeting (IEDM) Tech. Dig. Papers, Dec. 2009, pp