1. Principles & Applications
Digital Electronics
Principles & Applications
Seventh Edition
Roger L. Tokheim
Chapter 7
Flip-Flops
©2008 The McGraw-Hill Companies, Inc. All rights reserved.

2. INTRODUCTION Combinational vs. Sequential Logic Circuits R-S Flip-flop
Clocked R-S Flip-flop
D Flip-flop
J-K Flip-flop
Latches (simple memory devices)
Triggering of flip-flops
Schmitt triggered device

3. Logic Circuits Logic circuits are classified into two groups:
Combinational Logic Circuits
Basic building
blocks include:
Sequential Logic Circuits
Basic building blocks
include FLIP-FLOPS:

4. QUIZ
1. Basic building blocks for __________ (combinational, sequential) logic circuits include logic gates (such as NOT, AND, and OR).
combinational
2. Basic building blocks for sequential logic circuits include various flip-flops. (True or False)
True
3. A flip-flop is an example of a device used in __________ (combinational, sequential) logic circuits.
sequential

5. R-S Flip-Flop Symbols: Truth Table: Mode of Operation Inputs Outputs
Set
Reset S R Q
Normal
Comple-mentary FF
Truth Table:
Mode of Operation Inputs Outputs
S R Q Q’
Prohibited
Set
Reset
Hold Q Q’
NOTE: Active-LOW inputs

6. QUIZ
What is the mode of operation of the R-S flip-flop (set, reset or hold)?
What is the output at Q from the R-S flip-flop (active LOW inputs)?
Mode of operation = ? ? L H
High
Set
Mode of operation = ? ? H
High
Hold
Mode of operation = ? ? H L
Low
Reset

7. Clocked R-S Flip-Flop Symbols: Truth Table:
Set
Reset S R Q
Normal
Comple-mentary FF
Clock
CLK
Truth Table:
Mode of operation Inputs Outputs
Clk S R Q Q’
Hold pulse no change
Reset pulse
Set pulse
Prohibited
NOTE: Active-High inputs

8. QUIZ High Set High Hold Low Reset
What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?
What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)? H ^ L
Mode of operation = ? ?
High
Set L ^
Mode of operation = ? ?
High
Hold L ^ H
Mode of operation = ? ?
Low
Reset

9. D Flip-Flop Symbol: Truth Table: (with asynchronous PS & CLR)
Mode of Operation Inputs Outputs PS CLR CLK D Q Q’
Asynchronous set X X
Asynchronous reset X X
Prohibited X X
Set ^
Reset ^
X = irrelevant
^ = L-to-H transition of the clock pulse

10. QUIZ What is the mode of operation of the D flip-flop?
What is the output at Q from the D flip-flop? L H ^ ?
Mode of operation = ?
High
Asynchronous Set H L ^ ?
Mode of operation = ?
Low
Reset H ^ ?
Mode of operation = ?
High
Set

11. J-K Flip-Flop Symbol: Truth Table: Mode of Operation Inputs Outputs
PS Clr Clk J K Q Q’
Asynchronous set x x x
Asynchronous reset x x x
Prohibited x x x
Hold ^ no change
Reset ^
Set ^
Toggle ^ opposite
x = Irrelevant
^ = H-to-L transition of clock pulse

12. QUIZ What is the mode of operation of the J-K flip-flop?
What is the output at Q from the J-K flip-flop? L ^ H
Mode of
operation = ? ? H ^
Mode of
operation = ? ?
High
High
Preset
Toggle H ^
Mode of
operation = ? ?
Mode of
operation = ? H ^ ?
Low
Low
Toggle
Toggle
Mode of
operation = ? H L ^ ? H ^ L
Mode of
operation = ? ?
Low
Low
Reset
Clear

13. Latch A fundamental digital storage device
The act of storing data for a time, such as “to latch”
An R-S flip-flop is an example of a latch
A D flip-flop can perform as a latch
In IC form (examples: 4-bit, 8-bit, 9-bit, 10 bit)
Is commonly imbedded in complex ICs

14. QUIZ
1. A fundamental digital storage device is sometime called a(n) ___ (gate, latch).
latch
2. The job of a latch can be performed by a(n) ___ (gate, D-flip-flop).
D-flip-flop
3. We say that “to latch” is the act of storing data for a time. (True or False)
True
4. Latches are commonly imbedded in more complex ICs and serve as temporary memory devices. (True or False)
True

15. Triggering of Flip-Flops
Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is HIGH.
Edge-triggering is the transfer of data from input to output of a flip-flop on the rising edge (L-to-H) or falling edge (H-to-L) of the clock pulse. Edge triggering may be either positive-edge (L-to-H) or negative-edge (H-to-L). Master-slave triggering is an older technique using the whole clock pulse but think of a master-slave flip-flop as having negative-edge triggering.
Negative-edge triggering
Positive-edge triggering H L
time
Level triggering

16. QUIZ
1. If a flip-flop triggers on the L-to-H transition of the clock pulse (see A) it is called a __________ (level, positive-edge) triggered device.
positive-edge
2. If a flip-flop triggers on the H-to-L transition of the clock pulse (see B) it is called a __________ (level, negative-edge) triggered device.
negative-edge
3. If a flip-flop triggers while the clock pulse is HIGH (see C) it is called a __________ (level, positive-edge) triggered device.
level C B A H L
time

17. Schmitt Trigger Operation
Positive-going threshold
Negative-going threshold
Output
Input
Schmitt trigger device
“squares” up input

18. QUIZ
1. The symbol at the lower right is that of a __________ (magneto-optical, Schmitt trigger) inverter.
Schmitt trigger
2. If the input signal to the Schmitt trigger inverter is a sine wave the output will be a __________ (square-wave, triangular-wave).
square wave
3. A Schmitt-trigger device will “digitize” or square up input signals with slow rise times and slow fall times. (True or False)
True

19. REVIEW Combinational vs. Sequential Logic Circuits R-S Flip-flop
Clocked R-S Flip-flop
D Flip-flop
J-K Flip-flop
Latches (simple memory devices)
Triggering of flip-flops
Schmitt triggered device